research-article

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

Authors:

A. Chattopadhyay,

H. MeyrAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 7, Issue 4

Article No.: 40, Pages 1 - 31

https://doi.org/10.1145/1376804.1376808

Published: 01 August 2008 Publication History

Abstract

Modern application-specific instruction-set processors (ASIPs) face the daunting task of delivering high performance for a wide range of applications. For enhancing the performance, architectural features, for example, pipelining, VLIW, are often employed in ASIPs, leading to high design complexity. Integrated ASIP design environments, like template-based approaches and language-driven approaches, provide an answer to this growing design complexity. At the same time, increasing hardware design costs have motivated the processor designers to introduce high flexibility in the processor. Flexibility, in its most effective form, can be introduced to the ASIP by coupling a reconfigurable unit to the base processor. Because of its obvious benefits, several reconfigurable ASIPs (rASIPs) have been designed for years. This design paradigm gained momentum with the advent of coarse-grained FPGAs, where the lack of domain-specific performance common in general-purpose FPGAs are largely overcome by choosing application-dependent basic functional units. These rASIP designs lack a generic flow from high-level specification, resulting in intuitive design decisions and hard-to-retarget processor design tools. Although partial, template-based approaches for rASIP design is existent, a clear design methodology especially for the prefabrication architecture exploration is not present. In order to address this issue, a high-level specification and design methodology for partially reconfigurable VLIW processors is proposed in this article. To show the benefit of this approach, a commercial VLIW processor is used as the base architecture and two domains of applications are studied for potential performance gain.

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Cited By

Gan ZZhang MGu ZTan HZhang J(2017)Delay analysis and optimization for inter-core interference in real-time embedded multicore systemsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.12.004103:C(77-86)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1016/j.jpdc.2016.12.004
Gan ZZhang MGu ZZhang JTan H(2017)Minimizing Bank Conflict Delay for Real-Time Embedded Multicore Systems via Bank MappingSmart Computing and Communication10.1007/978-3-319-52015-5_2(12-21)Online publication date: 13-Jan-2017
https://doi.org/10.1007/978-3-319-52015-5_2

Index Terms

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors
1. Computer systems organization

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cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 7, Issue 4

July 2008

264 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/1376804

Issue’s Table of Contents

Copyright © 2008 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 August 2008

Accepted: 01 March 2008

Received: 01 August 2007

Published in TECS Volume 7, Issue 4

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Cited By

Gan ZZhang MGu ZTan HZhang J(2017)Delay analysis and optimization for inter-core interference in real-time embedded multicore systemsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.12.004103:C(77-86)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1016/j.jpdc.2016.12.004
Gan ZZhang MGu ZZhang JTan H(2017)Minimizing Bank Conflict Delay for Real-Time Embedded Multicore Systems via Bank MappingSmart Computing and Communication10.1007/978-3-319-52015-5_2(12-21)Online publication date: 13-Jan-2017
https://doi.org/10.1007/978-3-319-52015-5_2

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