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Practical weak-atomicity semantics for java stm

Published: 14 June 2008 Publication History

Abstract

As memory transactions have been proposed as a language-level replacement for locks, there is growing need for well-defined semantics. In contrast to database transactions, transaction memory (TM) semantics are complicated by the fact that programs may access the same memory locations both inside and outside transactions. Strongly atomic semantics, where non transactional accesses are treated as implicit single-operation transactions, remain difficult to provide without specialized hardware support or significant performance overhead. As an alternative, many in the community have informally proposed that a single global lock semantics [18,10], where transaction semantics are mapped to those of regions protected by a single global lock, provide an intuitive and efficiently implementable model for programmers.
In this paper, we explore the implementation and performance implications of single global lock semantics in a weakly atomic STM from the perspective of Java, and we discuss why even recent STM implementations fall short of these semantics. We describe a new weakly atomic Java STM implementation that provides single global lock semantics while permitting concurrent execution, but we show that this comes at a significant performance cost. We also propose and implement various alternative semantics that loosen single lock requirements while still providing strong guarantees. We compare our new implementations to previous ones, including a strongly atomic STM.[24]

References

[1]
M. Abadi, A. Birrell, T. Harris, and M. Isard. Semantics of transactional memory and automatic mutual exclusion. In POPL 2008.
[2]
A.-R. Adl-Tabatabai, B. T. Lewis, V. S. Menon, B. R. Murphy, B. Saha, and T. Shpeisman. Compiler and runtime support for efficient software transactional memory. In PLDI 2006.
[3]
S. Adve and K. Gharachorloo. Shared memory consistency models: A tutorial. IEEE Computer, 29(12):66--76, 1996.
[4]
C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded transactional memory. In HPCA 2005.
[5]
C. Blundell, E. C. Lewis, and M. M. K. Martin. Deconstructing transactions: The subtleties of atomicity. In Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking, 2005.
[6]
H. Boehm. A memory model for c++: Strawman proposal.In C++ standards committee paper WG21/N1942 February 2006. http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n1942.html.
[7]
H. Boehm. A memory model for c++: Sequential consistency for race-free programs. http://hpl.hp.com/personal/Hans Boehm/c++mm/D2335.html,August 2007.
[8]
D. Dice, O. Shalev, and N. Shavit. Transactional Locking II. In DISC 2006.
[9]
J. Gray and A. Reuter. Transaction Processing: Concepts and Techniques Morgan Kaufmann, 1993.
[10]
D. Grossman, J. Manson, and W. Pugh. What do high-level memory models mean for transactions? In MSPC 2006.
[11]
L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis,and K. Olukotun. Transactional memory coherence and consistency. In ISCA 2004.
[12]
T. Harris and K. Fraser. Language support for lightweight transactions. In OOPSLA 2003.
[13]
T. Harris, S. Marlow, S. P. Jones, and M. Herlihy. Composable memory transactions. In PPoPP 2005.
[14]
T. Harris, M. Plesko, A. Shinnar, and D. Tarditi. Optimizing memory transactions. In PLDI 2006.
[15]
R. L. Hudson, B. Saha, A.-R. Adl-Tabatabai, and B. C. Hertzberg. Mcrt-malloc: A scalable transactional memory allocator. In ISMM 2006.
[16]
Intel Corporation. Intel 64 Architecture Memory Ordering White Paper http://www.intel.com/products/processor/manuals/318147.pdf.
[17]
L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers 9(29):690--691, 1979.
[18]
J. Larus and R. Rajwar. Transactional Memory Morgan & Claypool Publishers, 2006.
[19]
J. Manson, W. Pugh, and S. V. Adve. The Java memory model. In POPL 2005.
[20]
V. Menon, S. Balensiefer, T. Shpeisman, A.-R. Adl-Tabatabai, R. L. Hudson, B. Saha, and A. Welc. Towards a lock-based semantics for Java STM. Technical Report UW--CSE--07--11--01, November 2007.
[21]
K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. LogTM: Log-based transactional memory. In HPCA 2006.
[22]
K. F. Moore and D. Grossman. High-level small-step operational semantics for transactions. In POPL 2008.
[23]
R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In ISCA 2005.
[24]
T. Shpeisman, V. Menon, A.-R. Adl-Tabatabai, S. Balensiefer, D. Grossman, R. L. Hudson, K. F. Moore, and S. Bratin. Enforcing isolation and ordering in stm. In PLDI 2007.
[25]
M. F. Spear, V. J. Marathe, L. Dalessandro, and M. L. Scott. Brief announcement: Privatization techniques for software transactional memory. In PODC 2007.
[26]
M. F.Spear, V. J. Marathe, L. Dalessandro, and M. L. Scott. Privatization techniques for software transactional memory. Technical Report 915, University of Rochester, Computer Science Dept., 2007.
[27]
H. Sutter. Prism -A Principle-Based Sequential Memory Model for Microsoft Native Code Platforms Draft Version 0.9.1. http://www.openstd.org/jtc1/sc22/wg21/docs/papers/2006/n2075.pdf, September 2006.
[28]
C. Wang, W.-Y. Chen, Y. Wu, B. Saha, and A.-R. Adl-Tabatabai. Code generation and optimization for transactional memory constructs in an unmanaged language. In CGO 2007.

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  • (2020)Brief Announcement: On Implementing Software Transactional Memory in the C++ Memory ModelProceedings of the 39th Symposium on Principles of Distributed Computing10.1145/3382734.3405746(224-226)Online publication date: 31-Jul-2020
  • (2019)Simplifying Transactional Memory Support in C++ACM Transactions on Architecture and Code Optimization10.1145/332879616:3(1-24)Online publication date: 25-Jul-2019
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cover image ACM Conferences
SPAA '08: Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
June 2008
380 pages
ISBN:9781595939739
DOI:10.1145/1378533
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 14 June 2008

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Author Tags

  1. java
  2. memory models
  3. programming language semantics
  4. transactional memory
  5. weak atomicity

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Overall Acceptance Rate 447 of 1,461 submissions, 31%

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Cited By

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  • (2023)Separating Mechanism from Policy in STM2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00031(279-296)Online publication date: 21-Oct-2023
  • (2020)Brief Announcement: On Implementing Software Transactional Memory in the C++ Memory ModelProceedings of the 39th Symposium on Principles of Distributed Computing10.1145/3382734.3405746(224-226)Online publication date: 31-Jul-2020
  • (2019)Simplifying Transactional Memory Support in C++ACM Transactions on Architecture and Code Optimization10.1145/332879616:3(1-24)Online publication date: 25-Jul-2019
  • (2019)Modular transactionsProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295708(82-93)Online publication date: 16-Feb-2019
  • (2017)Hybridizing and Relaxing Dependence Tracking for Efficient Parallel Runtime SupportACM Transactions on Parallel Computing10.1145/31081384:2(1-42)Online publication date: 30-Aug-2017
  • (2017)Hand-Over-Hand Transactions with Precise Memory ReclamationProceedings of the 29th ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3087556.3087587(255-264)Online publication date: 24-Jul-2017
  • (2017)Practical Experience with Transactional Lock Elision2017 46th International Conference on Parallel Processing (ICPP)10.1109/ICPP.2017.17(81-90)Online publication date: Aug-2017
  • (2016)Persistence programming models for non-volatile memoryACM SIGPLAN Notices10.1145/3241624.292670451:11(55-67)Online publication date: 14-Jun-2016
  • (2016)Languages Must Expose Memory HeterogeneityProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989122(251-256)Online publication date: 3-Oct-2016
  • (2016)Extending TM Primitives using Low Level SemanticsProceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures10.1145/2935764.2935794(109-120)Online publication date: 11-Jul-2016
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