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The adaptive transactional memory test platform: a tool for experimenting with transactional code for rock (poster)

Published: 14 June 2008 Publication History

Abstract

Sun has recently announced that its forthcoming multicore processor, code-named Rock, will support a form of hardware transactional memory (HTM). Our poster describes this feature, and presents the Adaptive Transactional Memory Test Platform (ATMTP)---a simulator we have developed that allows us and others to experiment with code that uses it, as well as the results of some preliminary experiments conducted using ATMTP.

References

[1]
D. Dice, M. Herlihy, D. Lea, Y. Lev, V. Luchangco, W. Mesard, M. Moir, K. Moore, and D. Nussbaum. Applications of the Adaptive Transactional Memory Test Platform. In The third annual ACM SIGPLAN Workshop on Transactional Computing, February 2008. http://research.sun.som/scalable/pubs/ TRANSACT2008-ATMTP-APPS.pdf.
[2]
M. Moir, K. Moore, and D. Nussbaum. The Adaptive Transactional Memory Test Platform: A tool for experimenting with transactional code for Rock. In The third annual ACM SIGPLAN Workshop on Transactional Computing, February 2008. http://research.sun.som/scalable/pubs/ TRANSACT2008-ATMTP.pdf.

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  • (2022)Error RecoveryFault Tolerant Computer Architecture10.1007/978-3-031-01723-0_3(61-79)Online publication date: 5-Mar-2022
  • (2020)Based on Reconfiguring the Supercomputers Runtime Environment New Security MethodsAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0503385:3(291-298)Online publication date: 2020
  • (2019)Enhancing transactional memory execution via dynamic binary translationACM SIGAPP Applied Computing Review10.1145/3325061.332506519:1(48-58)Online publication date: 8-Apr-2019
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Published In

cover image ACM Conferences
SPAA '08: Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
June 2008
380 pages
ISBN:9781595939739
DOI:10.1145/1378533
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 14 June 2008

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Author Tags

  1. multicore
  2. multiprocessors
  3. performance
  4. scalability
  5. simulation
  6. synchronization
  7. transactional memory

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SPAA08

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Overall Acceptance Rate 447 of 1,461 submissions, 31%

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Cited By

View all
  • (2022)Error RecoveryFault Tolerant Computer Architecture10.1007/978-3-031-01723-0_3(61-79)Online publication date: 5-Mar-2022
  • (2020)Based on Reconfiguring the Supercomputers Runtime Environment New Security MethodsAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0503385:3(291-298)Online publication date: 2020
  • (2019)Enhancing transactional memory execution via dynamic binary translationACM SIGAPP Applied Computing Review10.1145/3325061.332506519:1(48-58)Online publication date: 8-Apr-2019
  • (2018)Dynamic tuning of applications using restricted transactional memoryProceedings of the 2018 Conference on Research in Adaptive and Convergent Systems10.1145/3264746.3264789(249-254)Online publication date: 9-Oct-2018
  • (2013)IBM Blue Gene/Q memory subsystem with speculative execution and transactional memoryIBM Journal of Research and Development10.1147/JRD.2012.222809257:1(79-90)Online publication date: 1-Jan-2013
  • (2013)Robust architectural support for transactional memory in the power architectureACM SIGARCH Computer Architecture News10.1145/2508148.248594241:3(225-236)Online publication date: 23-Jun-2013
  • (2013)Robust architectural support for transactional memory in the power architectureProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485942(225-236)Online publication date: 23-Jun-2013
  • (2013)Implementation of Intel Restricted Transactional Memory ISA Extension in SimicsProcedia Computer Science10.1016/j.procs.2013.05.34918(1804-1813)Online publication date: 2013
  • (2012)OpenMP Application in TM-based Parallel ProgramProceedings of the 2012 International Conference on Computer Science and Electronics Engineering - Volume 0310.1109/ICCSEE.2012.281(599-603)Online publication date: 23-Mar-2012
  • (2011)Invited Paper: The Inherent Complexity of Transactional Memory and What to Do about ItDistributed Computing and Networking10.1007/978-3-642-17679-1_1(1-11)Online publication date: 2011
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