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A generalized network flow based algorithm for power-aware FPGA memory mapping

Authors:

Tien-Yuan Hsu,

Ting-Chi WangAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 30 - 33

https://doi.org/10.1145/1391469.1391479

Published: 08 June 2008 Publication History

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Abstract

In this paper, we present a generalized network flow based algorithm for power-aware FPGA memory mapping. Our algorithm not only maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint but also achieves minimum power consumption. The experimental results show that our algorithm was always able to efficiently generate optimal solutions for all test cases while an existing greedy method could do so only for about one third of the test cases.

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Cited By

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Lee JHu YMajumdar RHe LLi MLin Y(2010)Fault-tolerant resynthesis with dual-output LUTsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899791(325-330)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899791
Lee JHu YMajumdar RHe LMinming Li (2010)Fault-tolerant resynthesis with dual-output LUTs2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419873(325-330)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419873

Index Terms

A generalized network flow based algorithm for power-aware FPGA memory mapping
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 08 June 2008

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National Science Council Taiwan

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DAC '08

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SIGDA

DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Lee JHu YMajumdar RHe LLi MLin Y(2010)Fault-tolerant resynthesis with dual-output LUTsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899791(325-330)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899791
Lee JHu YMajumdar RHe LMinming Li (2010)Fault-tolerant resynthesis with dual-output LUTs2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419873(325-330)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419873

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Power-aware RAM mapping for FPGA embedded memory blocks

Power Consumption Calculation of AP-DCD Algorithm Using FPGA Platform

Clock Gated Low Power Memory Implementation on Virtex-6 FPGA

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