research-article

Analog placement based on hierarchical module clustering

Authors:

Shyh-Chang LinAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 50 - 55

https://doi.org/10.1145/1391469.1391484

Published: 08 June 2008 Publication History

Abstract

In analog layout design, it is very important to reduce the parasitic coupling effects and improve the circuit performance. Consequently, the most important device-level placement constraints are matching, symmetry, and proximity. However, many previous works deal with these constraints separately, and none of them mention how to handle different constraints simultaneously and hierarchically. In this paper, we first give a case study to show the needs of integrating these constraints in a hierarchical manner. Then, we present the first formulation for analog placement based on hierarchical module clustering. Our approach can handle analog placement with various constraint groups including matching, (hierarchical) symmetry, and (hierarchical) proximity groups. To our best knowledge, this is also the first work in the literature to handle floorplanning with the clustering constraint using the B*-tree based representation. Experimental results based on industrial analog designs show that our approach is very effective and efficient.

References

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Cited By

Xu PLi JHo TYu BZhu K(2024)Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473859
Zhu KChen HLiu MPan D(2023)Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal FlowIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323036742:8(2689-2702)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3230367
Thasreefa APatyal AChi HLin MChen H(2023)On Reducing LDE Variations in Modern Analog PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319930742:4(1268-1279)Online publication date: Apr-2023
https://doi.org/10.1109/TCAD.2022.3199307
Show More Cited By

Index Terms

Analog placement based on hierarchical module clustering
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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The EDA Consortium
IEEE/CASS/CANDE/CEDA
SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 June 2008

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National Science Council Taiwan

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DAC '08

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SIGDA

DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

Xu PLi JHo TYu BZhu K(2024)Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473859
Zhu KChen HLiu MPan D(2023)Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal FlowIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323036742:8(2689-2702)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3230367
Thasreefa APatyal AChi HLin MChen H(2023)On Reducing LDE Variations in Modern Analog PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319930742:4(1268-1279)Online publication date: Apr-2023
https://doi.org/10.1109/TCAD.2022.3199307
Chen HTurner WPan DRen H(2022)Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774766(160-165)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774766
Chen HTurner WSong SZhu KKokai GZimmer BGray CKhailany BPan DRen HBehjat LYang S(2022)AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET TechnologiesProceedings of the 2022 International Symposium on Physical Design10.1145/3505170.3511044(175-183)Online publication date: 13-Apr-2022
https://dl.acm.org/doi/10.1145/3505170.3511044
Budak APan DChen HZhu KLiu MAlawieh MZhang SShi WTang X(2022)CAD for Analog/Mixed‐Signal Integrated CircuitsAdvances in Semiconductor Technologies10.1002/9781119869610.ch3(43-60)Online publication date: 30-Sep-2022
https://doi.org/10.1002/9781119869610.ch3
Zhu KChen HLiu MTang XSun NPan DXie Y(2020)Effective analog/mixed-signal circuit placement considering system signal flowProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415625(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415625
Chen ZZhou HGu J(2019)Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain ComputingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317800(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317800
Lu YChang YChang Y(2018)WB-treesProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196137(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196137
Xu BBasaran BSu MPan DChu CBustany I(2018)Analog Placement Constraint Extraction and Exploration with the Application to Layout RetargetingProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178245(98-105)Online publication date: 25-Mar-2018
https://dl.acm.org/doi/10.1145/3177540.3178245
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