Clifford E. Cummings
ABSTRACT
The IEEE Std 1800-2005 SystemVerilog Standard added new implicit port instantiation enhancements that help accelerate top-level composition of large ASIC & FPGA Designs. This paper details the new .* and .name implicit port instantiation capabilities, the rules related to the use of these new enhancements, and how these enhancements offer concise RTL coding styles while enforcing stronger port-type checking.
- Clifford E. Cummings, "SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification," SNUG (Synopsys Users Group) September 2007 (Boston, MA), September 2007. Also available at http://www.sunburst-design.com/papersGoogle Scholar
- Clifford E. Cummings, "SystemVerilog Implicit Port Connections - Simulation & Synthesis," DesignCon 2005 (Santa Clara, CA), February 2005. Also available at http://www.sunburst-design.com/papersGoogle Scholar
- Erich Whitney, personal communication.Google Scholar
- "IEEE Standard Verilog Hardware Description Language," IEEE Computer Society, IEEE, New York, NY, IEEE Std 1364--2001Google Scholar
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Index Terms
- SystemVerilog implicit port enhancements accelerate system design & verification
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