Babu Turumella
ABSTRACT
Exhaustive property checking, design defect isolation and functional coverage measurement are some of the key challenges of design verification. This paper describes how an assertion based approach successfully addressed these challenges for the verification of an enterprise class chip-multi-threaded (CMT) SPARC™ microprocessor. Methodology and experiences are discussed and recommendations are made on how to incorporate this into the design verification process. Experience with using assertion checks for formal verification as well as simulation based verification is presented, which is part of over 100 person year design verification effort.
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Index Terms
- Assertion-based verification of a 32 thread SPARC™ CMT microprocessor
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