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High-performance timing simulation of embedded software

Published: 08 June 2008 Publication History

Abstract

This paper presents an approach for cycle-accurate simulation of embedded software by integration in an abstract SystemC model. Compared to existing simulation-based approaches, we present a hybrid method that resolves performance issues by combining the advantages of simulation-based and analytical approaches. In a first step, cycle-accurate static execution time analysis is applied at each basic block of a cross-compiled binary program using static processor models. After that, the determined timing information is back-annotated into SystemC for fast simulation of all effects that can not be resolved statically. This allows the consideration of data dependencies during run-time and the incorporation of branch prediction and cache models by efficient source code instrumentation. The major benefit of our approach is that the generated code can be executed very efficiently on the simulation host with approximately 90% of the speed of the untimed software without any code instrumentation.

References

[1]
K. Albers, F. Bodmann, and F. Slomka. Hierarchical Event Streams and Event Dependency Graphs: A New Computational Model for Embedded Real-Time Systems. In Proceedings of the 18th Euromicro Conference on Real-Time Systems (ECRTS), pages 97--106, 2006.
[2]
C. Cifuentes. Reverse Compilation Techniques. PhD thesis, Queensland University of Technology, 19. Nov. 1994.
[3]
CoWare Inc. CoWare Processor Designer. http://www.coware.com/PDF/products/ProcessorDesigner.pdf.
[4]
A. Donlin. Transaction Level Modeling: Flows and Use Models. In Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 75--80, 2004.
[5]
R. Henia, A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst. System Level Performance Analysis - the SymTA/S Approach. IEE Proceedings Computers and Digital Techniques, 152(2):148--166, March 2005.
[6]
IEEE Computer Society. IEEE Standard SystemC® Language Reference Manual, Mar. 2006.
[7]
Infineon Technologies AG. TC10GP Unified 32-bit Microcontroller-DSP - User's Manual, 2000.
[8]
Infineon Technologies Corp. TriCore#8482; 32-bit Unified Processor Core - Volume 1: v1.3 Core Architecture, 2005.
[9]
S. Kraemer, L. Gao, J. Weinstock, R. Leupers, G. Ascheid, and H. Meyr. HySim: A Fast Simulation Framework for Embedded Software Development. In Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 75--80, 2007.
[10]
S. Künzli, F. Poletti, L. Benini, and L. Thiele. Combining Simulation and Formal Methods for System-Level Performance Analysis. In Proceedings of the Design, Automation and Test in Europe (DATE) Conference, pages 236--241, 2006.
[11]
S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, S.-M. Moon, and C. S. Kim. An Accurate Worst Case Timing Analysis for RISC Processors. IEEE Transactions on Software Engineering, 21(7):593--604, 1995.
[12]
A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr, and A. Hoffmann. A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation. In Proceedings of the 39th Design Automation Conference (DAC), pages 22--27, 2002.
[13]
OPNET Technologies, Inc. http://www.opnet.com.
[14]
M. Oyamada, F. Wagner, M. Bonaciu, W. Cesário, and A. Jerraya. Software Performance Estimation in MPSoC Design. In Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 38--43, 2007.
[15]
K. Richter, M. Jersak, and R. Ernst. A Formal Approach to MpSoC Performance Verification. Computer, 36(4):60--67, 2003.
[16]
G. Schirner, A. Gerstlauer, and R. Dömer. Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. In Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 384--389, 2007.
[17]
J. Schnerr, O. Bringmann, and W. Rosenstiel. Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. In Proceedings of the Design, Automation and Test in Europe (DATE) Conference, pages 792--797, 2005.
[18]
A. Siebenborn, A. Viehl, O. Bringmann, and W. Rosenstiel. Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. In Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 32--37, 2007.
[19]
Synopsys, Inc. Synopsys Virtual Platforms. http://www.synopsys.com/products/designware/virtual_platforms.html.
[20]
L. Thiele, S. Chakraborty, and M. Naedele. Real-time Calculus for Scheduling Hard Real-Time Systems. In IEEE International Symposium on Circuits and Systems (ISCAS), volume 4, pages 101--104, 2000.
[21]
VaST Systems Technology. CoMET®. http://www.vastsystems.com/docs/CoMET_mar2007.pdf.
[22]
A. Viehl, M. Schwarz, O. Bringmann, and W. Rosenstiel. Probabilistic Performance Risk Analysis at System-Level. In Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 185--190, 2007.
[23]
A. Viehl, T. Schönwald, O. Bringmann, and W. Rosenstiel. Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design. In Proceedings of the Design, Automation and Test in Europe (DATE) Conference, pages 242--247, 2006.
[24]
T. Wild, A. Herkersdorf, and G.-Y. Lee. TAPES -- Trace-Based Architecture Performance Evaluation with SystemC. Design Automation for Embedded Systems, 10(2--3):157--179, Sept. 2005.

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  • (2020)Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and MeasurementsACM Transactions on Design Automation of Electronic Systems10.1145/343181426:3(1-33)Online publication date: 31-Dec-2020
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cover image ACM Conferences
DAC '08: Proceedings of the 45th annual Design Automation Conference
June 2008
993 pages
ISBN:9781605581156
DOI:10.1145/1391469
  • General Chair:
  • Limor Fix
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 June 2008

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Author Tags

  1. simulation acceleration
  2. software timing
  3. virtual prototypes

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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  • (2024)AI-based estimation of embedded software execution cycles in host-compiled simulation2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS62603.2024.10769196(1-6)Online publication date: 13-Nov-2024
  • (2022)An Accurate State Visualization of Multiplexed and PWM Fed Peripherals in the Virtual Simulators of Embedded SystemsApplied Sciences10.3390/app1206313712:6(3137)Online publication date: 18-Mar-2022
  • (2020)Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and MeasurementsACM Transactions on Design Automation of Electronic Systems10.1145/343181426:3(1-33)Online publication date: 31-Dec-2020
  • (2020)FirePerfProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378455(715-731)Online publication date: 9-Mar-2020
  • (2019)Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/331024924:3(1-23)Online publication date: 11-Mar-2019
  • (2019)InvadeSIM-A Simulation Framework for Invasive Parallel Programs and ArchitecturesModeling and Simulation of Invasive Applications and Architectures10.1007/978-981-13-8387-8_3(41-76)Online publication date: 31-May-2019
  • (2018)A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimationProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201717(452-457)Online publication date: 22-Jan-2018
  • (2018)Framework for Rapid Performance Estimation of Embedded Soft Core ProcessorsACM Transactions on Reconfigurable Technology and Systems10.1145/319580111:2(1-21)Online publication date: 26-Jul-2018
  • (2018)Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation2018 Forum on Specification & Design Languages (FDL)10.1109/FDL.2018.8524038(5-16)Online publication date: Sep-2018
  • (2018)A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297365(452-457)Online publication date: Jan-2018
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