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Multiprocessor performance estimation using hybrid simulation

Published: 08 June 2008 Publication History

Abstract

With the growing number of programmable processing elements in today's Multi Processor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware architecture and the software running on them is also increasing. In MPSoC development environment, changes in the hardware architecture can bring in extensive re-partitioning or re-parallelization of the software architecture. Fast and accurate functional simulation and performance estimation techniques are needed to cope with this co-design problem at the early phases of MPSoC design space exploration. The current paper addresses this issue by introducing a framework which combines hybrid simulation, cache simulation and online trace-driven replay techniques to accurately predict performance of programmable elements in an MPSoC environment. The resulting simulation technique can easily cope with the continuous re-organizations of software architectures during an Instruction Set Simulator (ISS) based design process. Experimental results show that this framework can improve system simulation speed by 3-5× on average while achieving accuracy closely comparable to traditional ISSes.

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    cover image ACM Conferences
    DAC '08: Proceedings of the 45th annual Design Automation Conference
    June 2008
    993 pages
    ISBN:9781605581156
    DOI:10.1145/1391469
    • General Chair:
    • Limor Fix
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 08 June 2008

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    Author Tags

    1. HySim
    2. MPSoC
    3. address recovery
    4. cache simulation
    5. cross replay
    6. hybrid simulation
    7. performance estimation

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    • (2019)InvadeSIM-A Simulation Framework for Invasive Parallel Programs and ArchitecturesModeling and Simulation of Invasive Applications and Architectures10.1007/978-981-13-8387-8_3(41-76)Online publication date: 31-May-2019
    • (2018)Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight TablesSystem Level Design from HW/SW to Memory for Embedded Systems10.1007/978-3-319-90023-0_16(197-209)Online publication date: 17-Apr-2018
    • (2015)Profiling and annotation combined method for multimedia application specific MPSoC performance estimationFrontiers of Information Technology & Electronic Engineering10.1631/FITEE.140023916:2(135-151)Online publication date: 6-Feb-2015
    • (2015)RAPITIMATEProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357175(635-642)Online publication date: 18-Oct-2015
    • (2015)A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable ArchitecturesApplied Reconfigurable Computing10.1007/978-3-319-16214-0_24(293-300)Online publication date: 31-Mar-2015
    • (2014)FALCONProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593138(1-6)Online publication date: 1-Jun-2014
    • (2013)A basic-block power annotation approach for fast and accurate embedded software power estimation2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2013.6673261(118-123)Online publication date: Oct-2013
    • (2013)An Efficient Cycle Accurate Performance Estimation Model for Hardware Software Co-DesignEmbedded and Real Time System Development: A Software Engineering Perspective10.1007/978-3-642-40888-5_8(213-234)Online publication date: 20-Nov-2013
    • (2012)Automatic generation of functional models for embedded processor extensionsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492784(304-307)Online publication date: 12-Mar-2012
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