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Design of a mask-programmable memory/multiplier array using G4-FET technology

Published: 08 June 2008 Publication History

Abstract

A G4-FET is a 4 gate transistor that combines both JFET and MOS characteristics in a single device that may be fabricated in a standard silicon-on-insulator (SOI) process. In doing so, it enables the conducting channel to be controlled vertically through MOS gates, as well as horizontally, through junction gates. Further, depending upon how it is biased, a single G4-FET can serve as either a not-majority logic gate or as a charge storage-based memory cell. This unique device offers tremendous potential for innovative gate arrays, where real estate can be traded-off between logic and memory functions. In this paper, we take a first look at a mask-programmable G4-FET array that depending upon metal personalization, can function either as a DRAM array or a multiplier.

References

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B. Dufrene, K. Akarvardar, S. Cristoloveanu, B. J. Blalock, P. Gentil, E. Kolawa, and M. M. Mojarradi. Investigation of the four-gate action in g4-fets. ACM Trans. Elec. Dev., 51(11):1931--1935, November 2004.
[2]
Semiconductor Industries Association. International technology roadmap for semiconductors. Technical report, 2006.
[3]
R. Zhang, P. Gupta, and N. Jha. Synthesis of majority and minority networks and its applications to qca, tpl and set based nanotechnologies. In Proceedings of the 18th Conference on VLSI Design, pages 229--234, January 2005.

Cited By

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  • (2011)Logic Design with Ambipolar DevicesRegular Nanofabrics in Emerging Technologies10.1007/978-94-007-0650-7_5(155-183)Online publication date: 24-Mar-2011
  • (2009)Novel library of logic gates with ambipolar CNTFETsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874775(622-627)Online publication date: 20-Apr-2009
  • (2009)Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090742(622-627)Online publication date: Apr-2009

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  1. Design of a mask-programmable memory/multiplier array using G4-FET technology

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      cover image ACM Conferences
      DAC '08: Proceedings of the 45th annual Design Automation Conference
      June 2008
      993 pages
      ISBN:9781605581156
      DOI:10.1145/1391469
      • General Chair:
      • Limor Fix
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 08 June 2008

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      Author Tags

      1. G4-FET
      2. gate array

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      Cited By

      View all
      • (2011)Logic Design with Ambipolar DevicesRegular Nanofabrics in Emerging Technologies10.1007/978-94-007-0650-7_5(155-183)Online publication date: 24-Mar-2011
      • (2009)Novel library of logic gates with ambipolar CNTFETsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874775(622-627)Online publication date: 20-Apr-2009
      • (2009)Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090742(622-627)Online publication date: Apr-2009

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