How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach

Nowadays, mobile devices are integrating an increasing variety of wireless communication standards, and each standard demands a multitude of modes. This tremendous diversity, combined with the increasing development-cost of deep-submicron silicon, desires highly flexible baseband implementations. The tier-2 SDR (Software Defined Radio) paradigm, where the entire baseband runs on programmable architectures, is very attractive to obtain the desired flexibility. Parallel ISP (Instruction Set Processor) based SDR baseband platforms have attracted extensive interest in recent years. However, such implementations typically come with a much lower energy-efficiency than traditional implementations as ASICs (Application Specific Integrated Circuits). This energy efficiency gap remains to be bridged in order to make SDR more pervasive. Importantly, the gap is becoming even more and more challenging in emerging high rate communication standards, such as 3GPP LTE, Mobile WiMAX and 802.11n. This situation demands disruptive innovations.