ABSTRACT
Traditional software-based diagnosis of failing chips typically identifies several lines where the failure is believed to reside. However, these lines can span across multiple layers and can be very long in length. This makes physical failure analysis difficult. In contrast, there are emerging diagnosis techniques that identify both the faulty lines as well as the neighboring conditions for which an affected line becomes faulty. In this paper, an approach is presented to improve failure localization by automatically analyzing the information associated with the outcome of diagnosis. Experimental results show a significant improvement in failure localization when this method is applied to 106 real IC failures.
- Semiconductor Industry Association, "The International Technology Roadmap for Semiconductors," 2005 edition.Google Scholar
- L. C. Wagner, "Failure Analysis of Integrated Circuits Tool and Techniques," Kluwer Academic Publishers, Chapter 1: Introduction, pp. 1--12, 1999.Google Scholar
- R. Desineni, O. Poku, and R. D. Blanton. "A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior," International Test Conference, p. 12.3, 2006.Google Scholar
- L. C. Wagner, "Failure Analysis of Integrated Circuits Tool and Techniques," Kluwer Academic Publishers, Chapter 11: Chemical Analysis, pp. 195--204, 1999.Google Scholar
- K. S. Wills and S. Perungulam, "Delayering Techniques: Dry Processes, Wet Chemical Processing and Parallel Lapping," Microelectronics Failure Analysis Desktop Reference, p. 446, 2004.Google Scholar
- D. Rusli, "Etching Method using an At Least Semi-Solid Media," www.patentstorm.us/patents/7098143-description.html.Google Scholar
- T. Haddock and S. Boddicker, "Failure Analysis of Integrated Circuits Tool and Techniques," Kluwer Academic Publishers, Chapter 9: Cross Section Analysis, pp. 159--174, 1999.Google Scholar
- L. C. Wagner, "Failure Analysis of Integrated Circuits Tool and Techniques," Kluwer Academic Publishers, Chapter 10: Inspection Techniques, pp. 175--194, 1999.Google Scholar
- B. Engel, E. Levine, J. Petrus and A. Shore, "The Art of Cross Sectioning," Microelectronics Failure Analysis Desktop Reference, p. 473, 2004.Google Scholar
- T. J. Vogels et al., "Progressive Bridge Identification," International Test Conference, pp. 309--318, 2003.Google Scholar
- S. Venkataraman and S. B. Drummonds, "A technique for logic fault diagnosis of interconnect open defects," VLSI Test Symposium, pp. 313--318, 2000. Google ScholarDigital Library
- G. Ontko, "Fault Isolation of Large Nets Using Bridging Fault Analysis," International Symposium for Testing and Failure Analysis, pp. 99--102, 2004.Google Scholar
- D. Bodoh, A. Blakely and T. Garyet, "Diagnostic Fault Simulation for the Failure Analyst," International Symposium for Testing and Failure Analysis, pp. 181--190, 2004.Google Scholar
- C. Hora and S. Eichenberger, "Towards High Accuracy Fault Diagnosis of Digital Circuits," International Symposium for Testing and Failure Analysis, pp. 47--51, 2004.Google Scholar
- S. Venkataraman and W. K. Fuchs, "A Deductive Technique for Diagnosis of Bridging Faults," International Conference on Computer-Aided Design, pp. 562--567, Nov. 1997. Google ScholarDigital Library
- R. D. Blanton, K. N. Dwarakanath, and R. Desineni, "Defect Modeling Using Fault Tuples," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 2450--2464, Nov. 2006. Google ScholarDigital Library
- www.si2.org/openeda.si2.org.Google Scholar
- www.cgal.org.Google Scholar
Index Terms
- Precise failure localization using automated layout analysis of diagnosis candidates
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