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Challenges in gate level modeling for delay and SI at 65nm and below

Published: 08 June 2008 Publication History

Abstract

In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.

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  • (2023)Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD58065.2023.10192158(1-4)Online publication date: 3-Jul-2023
  • (2023)Complete Timing Model of ECSM Lookup Table for CMOS Inverter2023 8th International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICICM59499.2023.10365827(10-15)Online publication date: 20-Oct-2023
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  1. Challenges in gate level modeling for delay and SI at 65nm and below

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    cover image ACM Conferences
    DAC '08: Proceedings of the 45th annual Design Automation Conference
    June 2008
    993 pages
    ISBN:9781605581156
    DOI:10.1145/1391469
    • General Chair:
    • Limor Fix
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 08 June 2008

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    Author Tags

    1. delay calculation
    2. gate characterization
    3. gate modeling

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    View all
    • (2024)Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing AnalysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339643243:12(4715-4725)Online publication date: 1-Dec-2024
    • (2023)Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD58065.2023.10192158(1-4)Online publication date: 3-Jul-2023
    • (2023)Complete Timing Model of ECSM Lookup Table for CMOS Inverter2023 8th International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICICM59499.2023.10365827(10-15)Online publication date: 20-Oct-2023
    • (2021)Modeling Multiple-Input Switching in Timing Analysis Using Machine LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300962440:4(723-734)Online publication date: Apr-2021
    • (2021)An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD52597.2021.9531284(1-6)Online publication date: 30-Aug-2021
    • (2018)A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2018.80(301-306)Online publication date: Jan-2018
    • (2015)PrimeTime web-based report analyzer (PTWRA) tool2015 6th Asia Symposium on Quality Electronic Design (ASQED)10.1109/ACQED.2015.7274035(203-208)Online publication date: Aug-2015
    • (2013)Extending pre-silicon delay models for post-silicon tasksProceedings of the 2013 IEEE 31st VLSI Test Symposium (VTS)10.1109/VTS.2013.6548901(1-6)Online publication date: 29-Apr-2013
    • (2011)Statistical characterization of standard cells using design of experiments with response surface modelingProceedings of the 48th Design Automation Conference10.1145/2024724.2024742(77-82)Online publication date: 5-Jun-2011
    • (2011)An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763254(1-6)Online publication date: Mar-2011
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