Masanori Kurimoto
ABSTRACT
Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.
- B. H. Calhoun, et al., "Standby Power Reduction Using Dynamic Voltage Scaling and Canary Flip-Flop Structures", IEEE J. Solid-State Circuits, vol.39, no.9, pp. 1504--1511, Sep., 2004.Google Scholar
Cross Ref
- M. Nomura, et al., "Delay and Power Monitoring Schemes for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes", IEEE J. Solid-State Circuits, vol.41, no.4, pp.805--814, Apr., 2006.Google ScholarCross Ref
- S. Das et al., "A Self-Tuning DVS Processor Using Delay-Error Detection and Correction", IEEE J. Solid-State Circuits, vol.41, no.4, pp.792--804, Apr., 2006.Google ScholarCross Ref
Index Terms
- Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling
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