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Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters

Published: 08 June 2008 Publication History

Abstract

Recent CAD methodologies of Design-for-Manufacturability (DFM) have naturally led to a significant increase in the number of process and layout parameters that have to be taken into account in design-rule checking. Methodological consistency requires that a similar number of parameters be taken into account during layout parasitic extraction. Because of the inherent variability of these parameters, the issue of efficiently extracting deterministic parasitic sensitivities with respect to such a large number of parameters must be addressed. In this paper, we tackle this very issue in the context of capacitance sensitivity extraction. In particular, we show how the adjoint sensitivity method can be efficiently integrated within a finite-difference (FD) scheme to compute the sensitivity of the capacitance with respect to a large set of BEOL parameters. If np is the number of parameters, the speedup of the adjoint method is shown to be a factor of np/2 with respect to direct FD sensitivity techniques. The proposed method has been implemented and verified on a 65nm BEOL cross section having 10 metal layers and a total number of 59 parameters. Because of its speed, the method can be advantageously used to prune out of the CAD flow those BEOL parameters that yield a capacitance sensitivity less than a given threshold.

References

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Cited By

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  • (2014)Calculation of Generalized Polynomial-Chaos Basis Functions and Gauss Quadrature Rules in Hierarchical Uncertainty QuantificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.229581833:5(728-740)Online publication date: May-2014
  • (2011)Efficient sensitivity-based capacitance modeling for systematic and random geometric variationsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950826(61-66)Online publication date: 25-Jan-2011
  • (2011)Multi-Dimensional Automatic Sampling Schemes for Multi-Point Modeling MethodologiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.215872130:8(1141-1151)Online publication date: 1-Aug-2011
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  1. Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters

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    cover image ACM Conferences
    DAC '08: Proceedings of the 45th annual Design Automation Conference
    June 2008
    993 pages
    ISBN:9781605581156
    DOI:10.1145/1391469
    • General Chair:
    • Limor Fix
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 08 June 2008

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    Author Tags

    1. adjoint method
    2. capacitance extraction
    3. sensitivity analysis

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    View all
    • (2014)Calculation of Generalized Polynomial-Chaos Basis Functions and Gauss Quadrature Rules in Hierarchical Uncertainty QuantificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.229581833:5(728-740)Online publication date: May-2014
    • (2011)Efficient sensitivity-based capacitance modeling for systematic and random geometric variationsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950826(61-66)Online publication date: 25-Jan-2011
    • (2011)Multi-Dimensional Automatic Sampling Schemes for Multi-Point Modeling MethodologiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.215872130:8(1141-1151)Online publication date: 1-Aug-2011
    • (2011)Fast statistical analysis of RC nets subject to manufacturing variabilities2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763012(1-6)Online publication date: Mar-2011
    • (2011)Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique2011 IEEE Custom Integrated Circuits Conference (CICC)10.1109/CICC.2011.6055331(1-4)Online publication date: Sep-2011
    • (2011)Efficient sensitivity-based capacitance modeling for systematic and random geometric variations16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)10.1109/ASPDAC.2011.5722262(61-66)Online publication date: Jan-2011
    • (2009)An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapesProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630110(770-775)Online publication date: 26-Jul-2009
    • (2008)A capacitance solver for incremental variation-aware extractionProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509601(662-669)Online publication date: 10-Nov-2008
    • (2008)Sensitivity computation of interconnect capacitances with respect to geometric parameters2008 IEEE-EPEP Electrical Performance of Electronic Packaging10.1109/EPEP.2008.4675916(209-212)Online publication date: Oct-2008

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