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Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

Published: 11 August 2008 Publication History

Abstract

A simple yet effective technique that aims at reducing the energy and latency overheads incurred during the wakeup period of MTCMOS circuits is presented in this paper. One or more high-Vth keepers are inserted in MTCMOS combinational logic to reduce the metastability time that causes excessive short circuit current during mode transition and to minimize spurious glitches at internal circuit nodes. Employing the proposed keeper insertion technique in a 16-bit MTCMOS adder, up to 17.5% average wakeup energy and 54.6% wakeup latency reductions are achieved with negligible runtime power and latency overheads, while maintaining the standby energy efficiency of the original MTCMOS design.

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Cited By

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  • (2021)Optimum sizing of the sleep transistor in MTCMOS technologyAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153882138(153882)Online publication date: Aug-2021
  • (2018)Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power SwitchesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.223350522:1(13-26)Online publication date: 29-Dec-2018
  • (2018)Design of General Purpose Microprocessor with an Improved Performance Self-Sleep Circuit2018 International Conference on Smart Systems and Inventive Technology (ICSSIT)10.1109/ICSSIT.2018.8748868(419-424)Online publication date: Dec-2018
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    cover image ACM Conferences
    ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design
    August 2008
    396 pages
    ISBN:9781605581095
    DOI:10.1145/1393921
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 August 2008

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    Author Tags

    1. leakage power
    2. mode transition
    3. power gating

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    View all
    • (2021)Optimum sizing of the sleep transistor in MTCMOS technologyAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153882138(153882)Online publication date: Aug-2021
    • (2018)Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power SwitchesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.223350522:1(13-26)Online publication date: 29-Dec-2018
    • (2018)Design of General Purpose Microprocessor with an Improved Performance Self-Sleep Circuit2018 International Conference on Smart Systems and Inventive Technology (ICSSIT)10.1109/ICSSIT.2018.8748868(419-424)Online publication date: Dec-2018
    • (2012)Power-Gating Noise Minimization by Three-Step Wake-Up PartitioningIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2011.216988959:4(749-762)Online publication date: Apr-2012

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