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Variation-aware gate sizing and clustering for post-silicon optimized circuits

Published: 11 August 2008 Publication History

Abstract

As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. This paper proposes a variation-aware methodology for the simultaneous gate sizing and clustering for post-silicon tuning with adaptive body biasing. The proposed methodology uses an accurate table look-up model and fully explores the interaction between gate sizing and optimal body bias based clustering. In addition, it is suitable for industrial test cases with tens of thousands gates. Our optimization methodology includes a body bias distribution alignment strategy to mitigate the impact of critical gates. In this way, the cluster's body bias voltage is not simply determined by only a few critical gates. We also prove the linear dependence between the mean of the body bias probability distribution and the gate size. Based on this, we further investigate a simultaneous sizing and re-clustering algorithm for better leakage savings. A circuit re-balancing and gate snapping scheme is then suggested to map the solution to a standard cell library. Compared with arecently-reported method, the proposed methodology can obtain on average 25.5% leakage saving at nearly the same run time.

References

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Cited By

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  • (2015)Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2015.7273501(122-127)Online publication date: Jul-2015
  • (2014)Parametric yield optimization using leakage-yield-driven floorplanning2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2014.6951860(1-6)Online publication date: Sep-2014
  • (2014)Variation Aware Design of Post-Silicon Tunable Clock BufferProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.95(1-6)Online publication date: 9-Jul-2014
  • Show More Cited By

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    cover image ACM Conferences
    ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design
    August 2008
    396 pages
    ISBN:9781605581095
    DOI:10.1145/1393921
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 11 August 2008

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    Author Tags

    1. body bias
    2. clustering
    3. optimization
    4. sizing
    5. variation

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    Cited By

    View all
    • (2015)Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2015.7273501(122-127)Online publication date: Jul-2015
    • (2014)Parametric yield optimization using leakage-yield-driven floorplanning2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2014.6951860(1-6)Online publication date: Sep-2014
    • (2014)Variation Aware Design of Post-Silicon Tunable Clock BufferProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.95(1-6)Online publication date: 9-Jul-2014
    • (2013)Maximizing yield in Near-Threshold Computing under the presence of process variation2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2013.6662148(1-8)Online publication date: Sep-2013
    • (2010)Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale EraProceedings of the IEEE10.1109/JPROC.2010.205723098:10(1718-1751)Online publication date: Oct-2010
    • (2010)Effect of Variations and Variation Tolerance in Logic CircuitsLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_3(83-108)Online publication date: 25-Oct-2010
    • (2009)Leakage reduction, delay compensation using partition-based tunable body-biasing techniquesACM Transactions on Design Automation of Electronic Systems10.1145/1562514.156252114:4(1-22)Online publication date: 28-Aug-2009

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