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An efficient test and characterization approach for nanowire-based architectures

Published: 01 September 2008 Publication History

Abstract

Evolutions in process design techniques have allowed the construction of atomic-scale structures like nanowires. These 10nm wires can be used in the construction of regular structures with stochastic assemble, and promise to have up to 2 orders of magnitude greater density when compared to advanced CMOS FPGAs build close to 20nm technology. On the other hand, cost-effective fabrication of nanowires demands a bottom-up approach. In other to characterize the wires, the present wire-by-wire test procedure calls for long test time due to the high number of wires that have to be tested. This way, this paper revises some test strategies and characterization procedures for nanowires imposed by the bottom-up approach, and proposes a new approach, based on the number of wires required to build logic gates and the component granularity in the final circuit to reduce the test and characterization time. Results show meaningful reduction of the test and characterization time when comparing the proposed approach with the wire-to-wire granularity approach. The work here presented proposes a new paradigm of test that bypasses the test and characterization procedures and goes right trough the programming phase. The test at the gate level is performed only after the programming phase We compare our results with the theoretical minimum that could be achieved for XOR gates.

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  • (2011)Using Quadded logic in nanoPLAs to aggressively increase circuit yieldThe 16th North-East Asia Symposium on Nano, Information Technology and Reliability10.1109/NASNIT.2011.6111143(180-185)Online publication date: Oct-2011

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  1. An efficient test and characterization approach for nanowire-based architectures

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    cover image ACM Conferences
    SBCCI '08: Proceedings of the 21st annual symposium on Integrated circuits and system design
    September 2008
    256 pages
    ISBN:9781605582313
    DOI:10.1145/1404371
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 01 September 2008

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    Author Tags

    1. characterization
    2. nanoPLA
    3. nanowires
    4. test
    5. yield

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    • (2011)Using Quadded logic in nanoPLAs to aggressively increase circuit yieldThe 16th North-East Asia Symposium on Nano, Information Technology and Reliability10.1109/NASNIT.2011.6111143(180-185)Online publication date: Oct-2011

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