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Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study

Published: 19 October 2008 Publication History

Abstract

Streaming applications can be implemented with a pipeline of processors. Each processor in the pipeline can be an application Specific Instruction Set Processor (ASIP) with the result being a heterogeneous pipelined MPSoC system. Since ASIPs can be of differing configurations, finding the optimal set of configurations for a multiprocessor architecture is a difficult problem.
In this paper, we obtain an optimal system design for a set of processors which execute a multimedia application. The variables in the system are the presence or absence of different additional instructions and differing cache configurations for each of the processors. The problem is formulated as a 0-1 Integer Linear Programming (ILP) problem. To reduce the complexity of the ILP formulation, inferior ASIP configurations are efficiently pruned so that the solution could be reached quickly. Given a system runtime constraint, the proposed methodology finds a design with minimal area. We integrated this design methodology into a commercial design flow, and performed a case study upon the JPEG encoding application. We obtained 15 optimal designs subject to 15 different runtime constraints, each in less than 100 seconds from more than 4.2 x 1013 design points.

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Cited By

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  • (2024)Optimized Multi-Processor System-on-Chip (MPSoC) Design for Low-Resource JPEG Encoding2024 6th International Conference on Advancements in Computing (ICAC)10.1109/ICAC64487.2024.10851123(115-120)Online publication date: 12-Dec-2024
  • (2018)System-level synthesis of multi-ASIP platforms using an uncertainty modelIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.00651:C(118-138)Online publication date: 28-Dec-2018
  • (2016)A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/279713521:2(1-32)Online publication date: 28-Jan-2016
  • Show More Cited By

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cover image ACM Conferences
CODES+ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
October 2008
288 pages
ISBN:9781605584706
DOI:10.1145/1450135
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 19 October 2008

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Author Tags

  1. MPSoCs
  2. design space exploration
  3. integer linear programming

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  • Research-article

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ESWEEK 08
ESWEEK 08: Fourth Embedded Systems Week
October 19 - 24, 2008
GA, Atlanta, USA

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CODES+ISSS '08 Paper Acceptance Rate 44 of 143 submissions, 31%;
Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

View all
  • (2024)Optimized Multi-Processor System-on-Chip (MPSoC) Design for Low-Resource JPEG Encoding2024 6th International Conference on Advancements in Computing (ICAC)10.1109/ICAC64487.2024.10851123(115-120)Online publication date: 12-Dec-2024
  • (2018)System-level synthesis of multi-ASIP platforms using an uncertainty modelIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.00651:C(118-138)Online publication date: 28-Dec-2018
  • (2016)A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/279713521:2(1-32)Online publication date: 28-Jan-2016
  • (2014)Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs)IEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2013.26825:8(2159-2168)Online publication date: Aug-2014
  • (2014)Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.229819633:5(663-676)Online publication date: May-2014
  • (2013)Multi-ASIP platform synthesis for real-time applications2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES)10.1109/SIES.2013.6601471(59-67)Online publication date: Jun-2013
  • (2013)Performance Estimation of Pipelined MPSoCsPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_4(65-83)Online publication date: 26-Nov-2013
  • (2013)Optimisation FrameworkPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_3(53-64)Online publication date: 26-Nov-2013
  • (2010)Rapid runtime estimation methods for pipelined MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871015(363-368)Online publication date: 8-Mar-2010
  • (2010)Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applicationsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1878961.1878978(75-84)Online publication date: 24-Oct-2010
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