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You can catch more bugs with transaction level honey

Published: 19 October 2008 Publication History

Abstract

In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to system-level diagnostics, ranging from use of most popular transaction level modeling languages through to hybrid technologies that combine TLMs with other well known diagnostic tools like in-silicon trace logic.

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cover image ACM Conferences
CODES+ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
October 2008
288 pages
ISBN:9781605584706
DOI:10.1145/1450135
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 October 2008

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Author Tags

  1. system diagnostics
  2. transaction-level models

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  • Research-article

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ESWEEK 08
ESWEEK 08: Fourth Embedded Systems Week
October 19 - 24, 2008
GA, Atlanta, USA

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CODES+ISSS '08 Paper Acceptance Rate 44 of 143 submissions, 31%;
Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

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  • (2013)Deterministic Replay Using Global ClockACM Transactions on Architecture and Code Optimization10.1145/2445572.244557310:1(1-28)Online publication date: 1-Apr-2013
  • (2013)LDetIEEE Transactions on Computers10.1109/TC.2012.11562:9(1732-1744)Online publication date: 1-Sep-2013
  • (2012)An enhanced debug-aware network interface for Network-on-ChipThirteenth International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2012.6187569(709-716)Online publication date: Mar-2012
  • (2011)Debug Aware AXI-based Network InterfaceProceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems10.1109/DFT.2011.34(399-407)Online publication date: 3-Oct-2011
  • (2010)LReplayACM SIGARCH Computer Architecture News10.1145/1816038.181598538:3(187-197)Online publication date: 19-Jun-2010
  • (2010)LReplayProceedings of the 37th annual international symposium on Computer architecture10.1145/1815961.1815985(187-197)Online publication date: 19-Jun-2010
  • (2009)On-chip transaction level debug support for system-on-chips2009 International SoC Design Conference (ISOCC)10.1109/SOCDC.2009.5423891(124-127)Online publication date: Nov-2009
  • (2009)Transaction-based debugging of system-on-chips with patterns2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413157(186-192)Online publication date: Oct-2009

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