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Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults

Published: 25 October 2008 Publication History

Abstract

To improve the lifetime performance of a multicore chip with simple cores, we propose the Core Cannibalization Architecture (CCA). A chip with CCA provisions a fraction of the cores as cannibalizable cores (CCs). In the absence of hard faults, the CCs function just like normal cores. In the presence of hard faults, the CCs can be cannibalized for spare parts at the granularity of pipeline stages. We have designed and laid out CCA chips composed of multiple OpenRISC 1200 cores. Our results show that CCA improves the chips' lifetime performances, compared to chips without CCA.

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          cover image ACM Conferences
          PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques
          October 2008
          328 pages
          ISBN:9781605582825
          DOI:10.1145/1454115
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          Published: 25 October 2008

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          Author Tags

          1. fault tolerance
          2. lifetime performance
          3. multicore
          4. reliability

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          View all
          • (2022)Self-RepairFault Tolerant Computer Architecture10.1007/978-3-031-01723-0_5(89-97)Online publication date: 5-Mar-2022
          • (2021)ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00051(520-532)Online publication date: Feb-2021
          • (2018)Efficient Performance Evaluation of Multi-Core SIMT Processors with Hot RedundancyIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.25949576:4(498-510)Online publication date: 1-Oct-2018
          • (2018)Parallel Error Detection Using Heterogeneous Cores2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN.2018.00044(338-349)Online publication date: Jun-2018
          • (2018)Thermoreflectance imaging of electromigration evolution in asymmetric aluminum constrictionsJournal of Applied Physics10.1063/1.5005938123:3Online publication date: 19-Jan-2018
          • (2017)Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital SystemsACM Computing Surveys10.1145/309269950:4(1-38)Online publication date: 4-Oct-2017
          • (2017)ANMR: Aging-aware adaptive N-modular redundancy for homogeneous multicore embedded processorsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2017.04.013109(29-41)Online publication date: Nov-2017
          • (2016)Faults in data prefetchers: Performance degradation and variability2016 IEEE 34th VLSI Test Symposium (VTS)10.1109/VTS.2016.7477312(1-6)Online publication date: Apr-2016
          • (2016)Resilient Chip Multiprocessors with Mixed-Grained ReconfigurabilityIEEE Micro10.1109/MM.2015.736:1(35-45)Online publication date: 1-Jan-2016
          • (2015)Lifetime Reliability Enhancement of MicroprocessorsACM Computing Surveys10.1145/278598848:1(1-25)Online publication date: 29-Sep-2015
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