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Opposite-phase register switching for peak current minimization

Published: 23 January 2009 Publication History

Abstract

In a synchronous sequential circuit, huge current peaks are often observed at the moment of clock transition (since all registers are clocked). Previous works focus on reducing the number of switching registers. However, even though the switching registers are the same, different combinations of switching directions still result in different peak currents. Based on that observation, in this article, we propose an ECO (engineering change order) approach to minimize the peak current by considering the switching directions of registers. Our approach is well suitable for reducing the peak current in IC testing. Experimental data consistently show that our approach works well in practice.

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Cited By

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  • (2015)Minimizing peak current in combinational circuit testJournal of Engineering Research10.7603/s40632-015-0012-93:2Online publication date: 24-Jun-2015
  • (2013)Low Power State Assignment Algorithm for FSMs Considering Peak Current OptimizationJournal of Computer Science and Technology10.1007/s11390-013-1397-228:6(1054-1062)Online publication date: 8-Nov-2013

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  1. Opposite-phase register switching for peak current minimization

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 14, Issue 1
    January 2009
    444 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/1455229
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 23 January 2009
    Accepted: 01 August 2008
    Revised: 01 October 2007
    Received: 01 May 2007
    Published in TODAES Volume 14, Issue 1

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    Author Tags

    1. IC testing
    2. Logic synthesis
    3. peak current
    4. sequential circuit synthesis

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    View all
    • (2015)Minimizing peak current in combinational circuit testJournal of Engineering Research10.7603/s40632-015-0012-93:2Online publication date: 24-Jun-2015
    • (2013)Low Power State Assignment Algorithm for FSMs Considering Peak Current OptimizationJournal of Computer Science and Technology10.1007/s11390-013-1397-228:6(1054-1062)Online publication date: 8-Nov-2013

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