A. Weinberger
ABSTRACT
Synopsis: The logical design of a parallel adder is developed which is capable of adding two 53-bit numbers in 1 micro-second. The design makes use of basically the same 1-megacycle circuitry which has been used successfully in the National Bureau of Standards' SEAC and DYSEAC computers. An analysis of the functional relationships of the carry digits to the augend and addend digits shows that it is feasible to form many carries simultaneously at the expense of relatively few components. The Boolean expressions for many successive carry digits can be expanded as explicit functions of some one lower-order carry, and of the relevant augend and addend digits. These somewhat complicated expressions are simplified by making substitutions for the common terms and factors they contain. These common terms and factors, called auxiliary carry functions, are implemented separately. All functional forms fit within the wide limits of gating complexity allowed by the type of circuitry to be used.
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Digital Library
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