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On memory system design

Published: 17 November 1970 Publication History

Abstract

A hierarchy of information accessibility exists in every system. Even simple calculators employ a two-level hierarchy consisting of internal registers and external key-entered data. In a typical computer system we find a multilevel hierarchy extending from working registers through random-access main-memory, to direct access devices, to sequential access devices, and on outward to off-line archives.

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S S Sisson M J Flynn Addressing patterns and memory handling algorithms AFIPS Proceedings Vol 33 FJCC 1968 pp 957--967
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G E BRYANT JOSS---A statistical summary AFIPS Proceedings Vol 31 FJCC 1967 pp 769--777

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cover image ACM Other conferences
AFIPS '70 (Fall): Proceedings of the November 17-19, 1970, fall joint computer conference
November 1970
683 pages
ISBN:9781450379045
DOI:10.1145/1478462
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • AFIPS: American Federation of Information Processing Societies

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 November 1970

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  • (1987)Line (block) size choice for CPU cache memoriesIEEE Transactions on Computers10.1109/TC.1987.500953736:9(1063-1076)Online publication date: 1-Sep-1987
  • (1983)Shared Cache for Multiple-Stream Computer SystemsIEEE Transactions on Computers10.1109/TC.1983.167612232:1(38-47)Online publication date: 1-Jan-1983
  • (1982)Analysis of Multiprocessors with Private Cache MemoriesIEEE Transactions on Computers10.1109/TC.1982.167599531:4(296-304)Online publication date: 1-Apr-1982
  • (1979)Program Behavior and the Performance of Interleaved MemoriesIEEE Transactions on Computers10.1109/TC.1979.167531928:3(191-199)Online publication date: 1-Mar-1979
  • (1979) PM 4 —A reconfigurable multiprocessor system for pattern recognition and image processing 1979 International Workshop on Managing Requirements Knowledge (MARK)10.1109/MARK.1979.8817082(255-266)Online publication date: Jun-1979
  • (1978)A New Solution to Coherence Problems in Multicache SystemsIEEE Transactions on Computers10.1109/TC.1978.167501327:12(1112-1118)Online publication date: 1-Dec-1978
  • (1977)Cache memory systems for multiprocessor architectureProceedings of the June 13-16, 1977, national computer conference10.1145/1499402.1499573(955-964)Online publication date: 13-Jun-1977
  • (1977)CPU-utilization and secondary-storage performanceProceedings of the June 13-16, 1977, national computer conference10.1145/1499402.1499552(819-825)Online publication date: 13-Jun-1977
  • (1976)Cache system design in the tightly coupled multiprocessor systemProceedings of the June 7-10, 1976, national computer conference and exposition10.1145/1499799.1499901(749-753)Online publication date: 7-Jun-1976
  • (1975)INFOPLEXProceedings of the May 19-22, 1975, national computer conference and exposition10.1145/1499949.1500067(581-586)Online publication date: 19-May-1975
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