David Casasent
ABSTRACT
On-line speech analysis systems are the subject of much intensive research. Spectral analysis of the speech pattern is an integral part of all such systems. To facilitate this spectral analysis and the associated preprocessing required, a special purpose fast Fourier transform (FFT) processor to be described is being designed and constructed. One unique feature of this processor which facilitates both its design and implementation while providing an easily alterable machine is its construction from standard logic modules which will be referred to throughout as register transfer modules or RTM's. This design approach results in a machine whose operation is easily understood due to this modular construction.
- C G Bell et al The description and use of register transfer modules (RTM's) IEEE Transactions on Computers Vol C-21 1972 Google Scholar
Digital Library
- R W Schafer L R Rabiner System for automatic formant analysis of voiced speech The Journal of the Acoustical Society of America Vol 47 No 2 1970Google Scholar
- E L Hall et al Generation of products and quotients using approximate binary logarithms for digital filtering application IEEE Transactions on Computers Vol C-19 1970 Google ScholarDigital Library
- G D Bergland A guided tour of the fast fourier transform IEEE Spectrum Vol 6 1969Google Scholar
- G D Bergland A fast fourier transform algorithm for real valued series Communications of the ACM Vol 11 1968 Google ScholarDigital Library
- B Gold et al The FDP, a fast programmable signal processor IEEE Transactions on Computers Vol C-20 No 1 1971 Google ScholarDigital Library
- J W Hartwell A procedure for implementing the fast fourier transform on small computers IBM Journal of Research and Development Vol 15 1971Google Scholar
- W W Moyer A high-speed indexing unit for FFT algorithm implementation Computer Design Vol 10 No 12 1971Google Scholar
- A register transfer module FFT processor for speech analysis
Recommendations
Design of FPGA Based Instruction Fetch & Decode Module of 32-bit RISC (MIPS) Processor
CSNT '11: Proceedings of the 2011 International Conference on Communication Systems and Network TechnologiesIn this paper, we analyze MIPS instruction format instruction data path decoder module function and design theory based on RISC CPU instruction set. Furthermore, we design instruction fetch (IF) module of 32-bit CPU based on RISC CPU instruction set. ...
Increasing Processor Performance Through Early Register Release
ICCD '04: Proceedings of the IEEE International Conference on Computer DesignModern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register files is to use smaller number of registers, but manage them more effectively. ...
A Series-parallel Mixed Structure FFT Processor
ICDSP '19: Proceedings of the 2019 3rd International Conference on Digital Signal ProcessingThe proposed fixed-point radix-2 decimation-in-time Fast Fourier Transform (R2DIT FFT) processor is implemented by the series-parallel mixed structure. The 64-point FFT is decomposed into 8-channel 8-point FFT structure. Each channel is a serial 8-point ...
Comments