A systematic approach to the design of digital bussing structures

A1 R L Alonso et al A multiprocessing structure Proceedings IEEE Computer Conference September 1967 pp 56--59 This paper describes a multiprocessor system with non-dedicated instruction and data busses. The control method is a simple decentralized daisy chain.

A2 S J Andelman Real-time I/O techniques to reduce system costs Computer Design May 1966 pp 48--54 This article describes two real-time I/O applications and how a computer is used in each. It also indicates the relationships among the system executive, the CPU computations, and the I/O data bus. It includes centralized bus control.

A3 J P Anderson et al D825---a multiple-computer system for command and control Proceedings FJCC 1962 AFIPS Press pp 86--96 This paper functionally describes the switch interlock system of the Burroughs D825 system. The switch is essentially a crossbar which can handle up to 64 devices. A priority-oriented bus allocation mechanism handles conflicting allocation requests. Priorities are preemptive.

A4 A Avizienis Design of fault-tolerant computers Proceedings FJCC 1967 AFIPS Press pp 733--743 This paper describes the internal structure of the JPL-STAR computer. The bus structure consists of two busses and two bus checkers. The busses transmit information in four-bit bytes and the bus checkers check for transmission errors.

B1 K E Batcher Sorting networks and their application Proceedings SJCC 1968 AFIPS Press pp 307--314 This paper describes various configurations of bitonic sorting networks which can be utilized as routing networks or permutation switches in multiprocessor systems.

B2 H R Beelitz System architecture for large-scale integration Proceedings FJCC 1967 AFIPS Press pp 185--200 This paper describes the architecture of LIMAC. It notes the hierarchical nature of bus structures, stating, "A local bus structure interconnects the sub-partitions of a functional module in the same sense that the machine bus interconnects all functional modules."

B3 R O Berg et al PEPE implementation study Honeywell Report 12251-FR Prepared for System Development Corporation under Subcontract SDC 71--61 This report contains an extensive bibliography of signal transmission papers and a survey of line drivers and receivers. It also describes the bus designs for the PEPE multiprocessor system.

B4 N A Boehmer et al Advanced avionic digital computer---arithmetic and control unit design Hughes Aircraft Report P70-517 prepared under Navy contract N62269-70-C-0534 December 1970 This report describes a main data bus design for the Advanced Avionic Digital Computer, including the bus communication and allocation mechanisms.

B5 F P Brooks K E Iverson Automatic data processing Wiley New York 1969 Section 5.4 Parameters of computer organization pp 250--262 This section discusses speed/cost/balance tradeoffs in computer architecture. Of specific interest is how bus width, speed, and degree of parallelism affect computer performance. Examples of tradeoff results are given in terms of the System/360.

B6 W Buchholz Planning a computer system McGraw-Hill New York 1962 Chapter 16 of this book describes the data exchange of the STRETCH computer. The data exchange is a switched bus which handles data flow among I/O and external storage units and the primary store. It is independent of CPU processes and able to function concurrently with the central processor.

B7 H B Burner et al A programmable data concentrator for a large computing system IEEE Transactions on Computers November 1969 pp 1030--1038 This paper describes the internal structure of a data concentrator to be used with an IBM 360/67. The concentrator utilizes an Interdata Model 4 computer. The details of the bus structure, including timing and control signals, are given. The system was built and utilized at Washington State University, Pullman, Washington.

C1 G N Cedarquist An input/output system for a multiprogrammed computer Report No 223 April 1967 Department of Computer Science University of Illinois This report describes the architecture of I/O systems, and deals with some parameters of bus structures through discussion of data transfers. It is primarily concerned with the implementation of centralized control and communication logic.

C2 Y C E Chen D L Epley Bounds on memory requirements of multiprocessing systems Proceedings 6th Annual Allerton Conference on Circuit and System Theory October 1968 pp 523--531 This paper presents a model of a multiprocessor with a multilevel memory. Given a computation graph with specified execution times and main memory requirements, bounds on the required main memory and the inter-memory channel rates are calculated. The trade-off between main memory size and backing memory channel capacity is discussed at some length.

C3 W W Chu A study of asynchronous time division multiplexing for time sharing computer systems Proceedings FJCC 1969 AFIPS Press pp 669--678 This paper describes the use of an asynchronous time division multiplexing system. A model is given which relates buffer size and queuing delays to traffic, number of lines, and burst lengths.

C4 W W Chu Demultiplexing considerations for statistical multiplexers IEEE Transactions on Computers June 1972 pp 603--609 This paper discusses tradeoffs and simulation results useful in the design of buffers used in a computer communication system. The tradeoffs between message lengths, buffer size, traffic intensity, etc., are considered.

C5 W W Chu A G Konheim On the analysis and modeling of a class of computer communication systems IEEE Transactions on Communications June 1972 pp 645--660 This paper derives models for a computer communication environment, applied to star and loop bus structure systems. The model provides a means of relating statistical parameters for traffic intensities, message lengths, etc.

C6 N Clark A C Gannet Computer-to-computer communication at 2.5 megabit/sec Proceedings of IFIP Congress 62 North Holland Publishing Company September 1962 pp 347--353 This paper describes an experimental synchronous high speed (2.5 megabit/second) communication system. It indicates the relationships of all system parts necessary to communicate in a party-line fashion among three computers.

C7 COLLINS RADIO CORPORATION C-system overview 523-0561644-001736 Dallas Texas October 1 1969 This brochure describes the architecture of the Collins C-System, especially the design and features of the Time Division Exchange (TDX) loop. The TDX loop is a 32 million bit-per-second serial communication link. Communication between devices is at a 2 million word-per-second rate. The system as initially implemented contained 16 channels, with expansion to a 512 million bit-per-second capability envisioned.

C8 M E Conway A multiprocessor system design Proceedings FJCC 1963 AFIPS Press pp 139--146 This paper describes the design of a multiprocessor system which used a matrix switch (called a memory exchange) to connect processors to memories. The unique feature of the configuration is that an associative memory is placed between each processor and the memory exchange for addressing purposes.

C9 A J Critchlow Generalized multiprocessing and multiprogramming systems Proceedings FJCC 1963 AFIPS Press pp 107--126 This paper describes the state of development of multiprocessor systems in 1963. There were essentially three bus schemes in use: the crossbar switch (Burroughs D825), the multiple bus (CDC-3600) and the time-shared bus (IBM STRETCH). Functional descriptions of the bus concepts are presented.

D1 R L Davis et al A building block approach to multiprocessing Proceedings FJCC 1972 AFIPS Press pp 685--703 This paper describes a bus structure (called a Switch Interlock) for use in a multiprocessor. It discusses the tradeoffs in choosing the structure, and looks at single bus, multiple bus, multiport, and crossbar systems. The Switch Interlock is a dedicated bus matrix switch which supports both single word and block transfers. The switch is designed to be implemented for bus widths from bit-serial to fully word-parallel.

D2 A J Deerfield Architectural study of a distributed fetch computer NAECON 1971 Record pp 214--217 This paper describes the distributed fetch computer in which the fetch (procedure and data) portion of the machine is distributed to the memory modules.

D3 A J Deerfield et al Distributed fetch computer concept study Air Force Contract No F-71-C-1417 February 1972 This report describes the design of a bus structure for use in the distributed fetch computer. This machine repartitions the fetch and execute portions of the processor in a multiprocessor system. The fetch units are associated with the memories instead of being with the execute units, thus decreasing bus traffic.

D4 A J Deerfield et al Interim report for arithmetic and control logic design study Navy Contract N62269-72-C-0023 May 1972 This report describes a proposed bus structure for the Advanced Avionic Digital Computer and some of the tradeoffs considered during the design.

D5 J B Dennis S S Patil Computation structures Chapter 4---Asynchronous Modular Systems MIT Department of Electrical Engineering Cambridge Massachusetts This chapter describes the reasons for asynchronous systems, and gives examples of asynchronous techniques and their timing mechanisms. It is useful in understanding asynchronous communications.

D6 E W Devore D H Lander Switching in a computer complex for I/O flexibility 1964 NEC pp 445--447 This paper describes the IBM 2816 Switching Unit, the bus system utilized to interconnect CPU's and tape drives. It discusses the modularity tradeoffs made in the 2816.

D7 DIGITAL EQUIPMENT CORPORATION PDP-11 handbook Chapter 8---Description of the UNIBUS pp 59--68 Maynard Massachusetts 1969 This chapter of the PDP-11 user's manual describes the UNIBUS functionally as a subsystem of the PDP-11. Data transfer operations performed by the bus are described and illustrated with examples, along with general concepts of bus operation and control.

D8 DIGITAL EQUIPMENT CORPORATION PDP-11 interface Application Note Maynard Massachusetts This document gives a brief description of the PDP-11 UNIBUS, a single undedicated bus with centralized daisy-chain control and fully-interlocked request/acknowledge communication.

D9 DIGITAL EQUIPMENT CORPORATION PDP-11 unibus interface manual DEC-11-HIAB-D Maynard Massachusetts 1970 This manual gives a detailed description of the PDP-11 UNIBUS, its operation in the computer, and methods for interfacing peripheral equipment to the bus.

D10 S B Dinman Direct function processor concept for system control Computer Design March 1970 pp 55--60 This article describes the (patented) GRI-909 bus structure. The machine consists of a series of functional modules strung between two undedicated busses with a bus modifier unit (which serves a function similar to the alpha code on the Harvard MARK IV). The GRI-909 is quite similar to the DEC PDP-11.

F1 K Fertig B C Duncan A new high-speed general purpose input/output mechanism with real-time computing capability Proceedings FJCC 1967 AFIPS Press pp 281--289 This paper describes techniques for I/O processing of self-clocked data utilizing phase locked loops.

F2 H Frank et al Computer communication network design---experience with theory and practice SJCC 1972 AFIPS Press pp 255--270 This paper describes the ARPANET design from the vantage point of two years experience with the message switching system. ARPANET is a store and forward message switching network in which a device interfaces into the system by means of an interface message processor (IMP). The IMP then routes the message through the network topology. This paper provides insight into the design and specification of dedicated "store-and-forward" message switching systems.

G1 E C Gangl Modular avionic computer NAECON 1972 Record pp 248--251 This paper describes the architecture of a modular computer including its internal bus structure. The bus consists of four parallel segments: a data bus, a status bus, a microprogrammed command bus, and a power distribution bus.

G2 D H Gibson Considerations in block oriented systems design Proceedings SJCC 1967 AFIPS Press pp 75--80 This paper describes the rationale and techniques for block transfers between CPU and memory. The study is to determine the affect of block size on CPU throughput.

G3 A I Groudan The SKC-2000 advanced aerospace computer NAECON 1972 Record pp 229--235 This paper describes the SKC-2000 computer and its internal bus structure. The bus operates in a request/acknowledge mode of communication and can handle devices of different speeds from 1 microsecond to larger than a millisecond with no design changes.

G4 H W Gschwind Design of digital computers Communications in Digital Computer Systems Chapter 8 Section 5 Springer-Verlag New York 1967 pp 347--367 This section describes computer I/O and access paths (busses) in terms of their communication ramifications. It points out that "even experts failed to look at computers seriously from a communication point of view for a surprisingly long time." It also details the communication that occurs in some general computer configurations.

G5 D C Gunderson Multi-processor computing apparatus U S Patent 3521238 July 13 1967 This patent describes a method of bussing in a multiprocessor system based upon the use of an associative switch. This bus scheme allows processors to access a centralized system memory by either location or some property of the data (content addressability). Each processor has its own individual access to the system memory so the bus is very reliable.

H1 M L Hanson Input/output techniques for computer communication Computer Design June 1969 pp 42--47 This article describes the I/O systems in several UNIVAC machines, and considers the types of data transfers, staus words, number of lines, method of operation, etc., of these bus structures.

H2 R H Hardin Self sequencing data bus technique for space shuttle Proceedings Space Shuttle Integrated Electronic Conference Vol 2 1971 pp 111--139 This presentation describes the design of SLAT (Slot Assigned TDM), a data bus for space shuttle. SLAT is a synchronous bus with global plus local synchronization. The requirements, length, control method, clock skew, and synchronization tradeoffs are discussed.

H3 H Hellerman Digital computer system principles Data Flow Circuits and Magnetic-Core Storage McGraw-Hill New York 1967 Chapter 5 pp 207--235 This chapter contains a discussion of data flow or bus circuits, with special emphasis on the trade-offs possible between economy and speed. The author stresses the fact that the bus organization of a computer is a major factor determining its performance.

H4 G P Hyatt Digital data transmission Computer Design Vol 6 No 11 November 1967 pp 26--30 This article deals primarily with the transmission of data in a synchronous bus structure. It considers in detail the clock skew problem, and describes propagation delay and mechanization problems. It concludes that the clock pulse should not be daisy-chained, but radially distributed, and that the sum (worst case) of data propagation delays must be less than the clock pulse period.

I1 F Inose et al A data highway system Instrumentation Technology January 1971 pp 63--67 This article describes a data bus designed to interface many digital devices together. The system is essentially a nondedicated single bus with one wire for data and another for addresses. The system is connected together in a "loop configuration." It uses a "5-value pulse" for synchronization, etc. The system has an access time of 200 microseconds and can handle 100 devices on a bus up to 1 kilometer in length.

K1 J C Kaiser J Gibbon A simplified method of transmitting and controlling digital data Computer Design May 1970 pp 87--91 This article treats the tradeoffs between the number of parallel lines in a bus and the complexity of gating at the bus destinations. The authors develop a matrix switch concept as a data exchange under program control. The programmed instruction thus is able to dynamically interconnect system elements by coded pulse coincidence control of the switching matrix.

K2 H Kaneko A Sawai Multilevel PCM transmission over a cable using feedback balanced codes NEC 1967 pp 508--513 This paper describes a multilevel PCM code (Feedback Balanced Code) suitable for transmission of data on a coaxial transmission cable.

K3 L J Koczela Distributed processor organization Advances in Computers Vol 19 Chapter 7 Communication Busses Academic Press New York 1968 pp 346--349 This author presents a functional description of a bussing scheme for a distributed cellular computer. Each processor can address its own private memory plus bulk storage. Communication between cells takes place over the bus in two modes: Local (between two cells) and Global (controller call plus one or more controlled cells). The intercell bus is used for both instructions and data; all transfers are set up and directed by the controller cell by means of eight bus control commands.

K4 G A Korn Digital computer interface systems Simulation December 1968 pp 285--298 This paper is a tutorial on digital computer interfaces. It begins with the party line I/O bus, and covers how devices are controlled, how interrupts are handled, and how data channels operate. It discusses the overall subject of interfaces (I/O and bussing system) from the systems point of view, describing how the subsystems all relate to each other.

L1 J R Land Data bus concepts for the space shuttle Proceedings Space Shuttle Integrated Electronic Conference Vol 3 1971 pp 710--785 This presents the space shuttle data management computer architecture from a bus-oriented viewpoint. It discusses the properties and design characteristics of the bus structures, and summarizes the design and mechanization trade-offs.

L2 F J Langley A universal function unit for avionic and missile systems NAECON Record 1971 pp 178--185 This paper discusses some trade-offs in computer architectures, and categorizes some architectures by their bus structures, providing an example for each category. It considers single time-shared bus systems, multiple bus systems, crossbar systems, dual bus external ensemble systems, multiple-bus integrated ensemble systems, etc.

L3 R Larkin A mini-computer multiprocessing system Second Annual Computer Designers Conference Los Angeles California February 1971 pp 231--235 The topology of communication between computer subsystems is discussed. Six basic topologies for communication internal to a computer are described: (1) radial, (2) tree, (3) bus, (4) matrix, (5) iterative, and (6) symmetric. Some topological implications of bus structures are discussed including the need to insure positive (one device) control of the bus during its transmission phase. All six topologies can be expressed in terms of dedicated and non-dedicated bus structures.

L4 S E Lass A fourth generation computer organization Proceedings SJCC 1968 AFIPS Press pp 435--441 This paper functionally describes the internal organization of a "fourth-generation" computer including its data channels and I/O bus structure.

L5 A L Leiner Buffering between input/output and the computer Proceedings FJCC 1962 pp 22--31 This paper describes the tradeoffs in synchronizing devices, and considers solutions to the problem of buffering between devices of different speeds.

L6 K N Levitt A study of data communication problems in a self-repairable multiprocessor Proceedings SJCC 1968 AFIPS Press pp 515--527 This paper presents a method of aerospace multiprocessor reliability enhancement by dynamic reconfiguration using busses which are data commutators. Two realizations of such a bus technique are permutation switching networks and crossbar switches.

L7 S Y Levy Systems utilization of large-scale integration IEEE Transactions on Computers Vol EC-16 No 5 1967 pp 562--566 This paper describes a new approach to computer organization based on LSI technology, employing functional partitioning of both the data path and control. Of particular interest is the data bus structure of an RCA Laboratories experimental machine using LSI technology.

L8 W A Levy E W Veitch Design for computer communication systems Computer Design January 1966 pp 36--41 This article relates memory size considerations to a user's wait time for a line to the memory. It is applicable to bus bandwidth design in the analysis of buffer sizes needed to load up a bus structure.

L9 R C Lutz PCM using high speed memory system for switching applications Data and Communication Design May-June 1972 pp 26--28 This article details a method of replacing a crossbar switch with a memory having an input and output commutation system and some counting logic. Advantages of this approach are low cost and linear growth.

M1 J S Mayo An approach to digital system network IEEE Transactions on Communication Technology April 1967 pp 307--310 This paper deals with synchronizing communication between devices with unlocked clocks. A system with frame sync is postulated and the number of bits necessary for efficient pulse stuffing is derived.

M2 J D Meng A serial input/output scheme for small computers Computer Design March 1970 pp 71--75 This article describes the trade-offs and results of designing an I/O data bus structure for a minicomputer.

M3 J S Miller et al Multiprocessor computer system study NASA Contract No 9-9763 March 1970 This report reviews the number and type of busses used in several computing systems such as: CDC 6000, IBM DCS, IBM 360 ASP series, IBM 4-Pi, Burroughs D825 and 5500, etc. It goes on to suggest the design of a multiprocessor for a space station. In particular the system has two busses, one for I/O and one for internal transfers. Specifically described are: message structure, access control, error checking and required bandwidth. A 220 MHz bandwidth requirement is deduced.

M4 W F Miller R Aschenbrenner The GUS multicomputer system IEEE Transactions on Computers December 1963 pp 671--676 This paper describes an Argonne Lab experimental computer with several memory and processing subsystems. All internal memory communication is handled by the Distributor, which functions as a data exchange and is expandable. No detailed description of the Distributor operation is furnished.

M5 R C Minnick et al Cellular bulk transfer systems Air Force Contract No F19628-67-C-0293 3 AD683744 October 1968 Part C of this report describes a bulk transfer system composed of an input array, an output array, and a mapping device. The mapping device moves data from the input to the output array and may contain logic. Simple bulk transfer systems are described which perform permutation on the data during its mapping.

P1 P E Payne A method of data transmission requiring maximum turnaround time Computer Design November 1968 p 82 This article describes a method of controlling data transmission between devices by polling.

P2 M Pirtle Intercommunication of processors and memory Proceedings FJCC 1967 AFIPS Press pp 621--633 This paper discusses the throughput of several different bus structures in a system configuration with the intent of providing the appropriate amount of memory bandwidth. It describes the allocation sequence of a typical bus, and concludes that it can be very effective to assign ". priorities to requests, rather than to processors and busses .. with memory systems which provide ample memory bus bandwidth to the processors."

P3 W W Plummer Asynchronous arbiters Computation Structures Group Memo No 56 MIT Project MAC February 1971 This memo describes logic for determining which of several requesting CPU's get access and in what order to a memory. It is potentially a portion of the control logic for a bus structure, and describes several different algorithms for granting access.

Q1 J T Quatse et al The external access network of a modular computer system Proceedings SJCC 1972 AFIPS Press pp 783--790 This paper describes the External Access Network (EAN), a switching network designed to interface processors to processors, processors to facilities, and memory to facilities in a modular time sharing system (PRIME) being built at Berkeley. The EAN acts like a crossbar switch or data exchange, and consists of processor, device, and switch nodes. To communicate, a processor selects an available switch node and connects the appropriate device node to it.

R1 R Rice W R Smith SYMBOL---a major departure from classic software dominated Von Neumann computing systems Proceedings SJCC 1971 AFIPS Press pp 575--587 This paper describes a functionally designed bus-oriented system. The system bus consists of 200 interconnection lines which run the length of the mainframe.

R2 R Rinder The input/output architecture of minicomputers Datamation May 1970 pp 119--124 This article surveys the architecture of minicomputer I/O units. It describes a typical I/O bus and the lines of information it would carry.

R3 M P Ristenbatt D R Rothschild Asynchronous time multiplexing IEEE Transactions on Communication Technology June 1968 pp 349--357 This paper describes the use of "asynchronous time multiplexing" techniques on analog data. Basically, the paper describes a synchronous system with non-dedicated time slots.

R4 K Roedl R Stoner Unique synchronizing technique increases digital transmission rate Electronics March 15 1963 pp 75--76 This note provides a method of synchronizing two devices having local clocks of supposedly equal frequencies.

R5 K K Roy Cellular bulk transfer system PhD Thesis Montana State University Bozeman Montana March 1970 Bulk transfer systems composed of input logic, output logic, and a mapping device are studied. The influences of mapping device, parallelism, etc., are considered.

S1 T Saito H Inose Computer simulation of generalized mutually synchronized systems Symposium on Computer Processing in Communications Polytechnic Institute of Brooklyn April 1969 pp 559--577 This paper describes ten ways to mutually synchronize devices having separate clocks so that data can be accurately delivered in the correct time slot of a synchronous system. The results of the simulation relate to the stability of the synchronizing methods.

S2 J Santos M I Otero On transferences and priorities in computer networks Symposium on Computers and Automata Vol 21 1971 pp 265--275 The structure of bus (channel) controllers is considered using the language of automata theory. The controller is decomposed into two units: one receives requests and availability signals, and generates corresponding requests to the other unit which allocates the bus on a priority basis. Both units are further decomposed into subunits.

S3 J W Schwartz Synchronization in communication satellite systems NEC 1967 pp 526--527 This paper describes tradeoffs and potential solutions to the clock skew problem in a widely dispersed system.

S4 C D Smith Optimization of design parameters for serial TDM Computer Design January 1972 pp 51--54 This article derives analytical tools for the analysis and optimization of a synchronous system with global plus local timing.

S5 D J Spencer Data bus design techniques NASA TM-X-52876 Vol VI pp 95--113 This paper discusses design alternatives for a multiplexed data bus to reduce point-to-point wiring cost and complexity. The author investigates coupling, coding, and control factors for both low and high signal-to-noise ratio lines for handling a data rate less than five million bits per second.

S6 D C Stanga Univac 1108 multiprocessor system Proceedings SJCC 1971 AFIPS Press pp 67--74 This paper describes how memory accesses are made from the multiple processors to the multiple memory banks in the 1108 multiprocessor system. It gives a block diagram of the system interconnectivity and describes how the multiple module access units operate to provide multiple access paths to a memory module.

S7 D J Stigliani et al Wavelength division multiplexing in light interface technology AD-721085 March 1971 This report describes the fabrication of a five-channel optical multiplexed communication line, and suggests some alternatives for matching wavelength multiplexed light transmission times to digital electrical circuits.

S8 J N Sturman An iteratively structured general purpose digital computer IEEE Transactions on Computers January 1968 pp 2--9 This paper describes a bus and its use in an iterative computer. The system is a dual dedicated bus structure with centralized control.

S9 J N Sturman Asynchronous operation of an iteratively structured general purpose digital computer IEEE Transactions on Computers January 1968 pp 10--17 This paper describes the synchronization of an iterative structure computer. The processing elements are connected on a common complex symbol bus. To allow asynchronous operation, a set of timing busses are added to the system common complex symbol bus. The timing busses take advantage of their transmission line properties to provide synchronism of the processors.

T1 F W Thoburn A transmission control unit for high speed computer-to-computer communication IBM Journal of Research and Development November 1970 pp 614--619 This paper describes a multiplex bus system for connecting a large number of computers together in a star organization. Special emphasis is given to the transmission control unit, a microprogrammed polling and interface unit which uses synchronous two-frequency modulation and a serializer/de-serializer unit.

T2 K J Thurber Programmable indexing networks Proceedings SJCC 1970 AFIPS Press pp 51--58 This paper describes data routing networks designed to perform a generalized index on the data during the routing process. The indexing networks map an input vector onto an output vector. The mapping is arbitrary and programmable. Several different solutions are presented with varying hardware, speed, and timing requirements. The networks are described in terms of shift register implementations.

T3 K J Thurber Permutation switching networks Proceedings of the 1971 Computer Designer's Conference Industrial and Scientific Conference Management Chicago Illinois January 1971 pp 7--24 This paper describes several permutation networks designed to provide a programmable system capable of interconnecting system elements. The networks are partitioned for LSI implementation and can be utilized in a pipeline fashion. Algorithms are given to determine a program to produce any of the N! possible permutations of N input lines.

T4 K J Thurber et al Master executive control for AADC Navy Contract N62269-72-C-0051 June 18 1972 This report describes a systematic approach to the design of digital bus structures and applies this tool to the design of a bus structure for the Advanced Avionic Digital Computer. The structure is designed with three major requirements: flexibility, modularity, and reliability.

T5 A Turczyn High speed data transmission scheme Proceedings 3rd Univac DPD Research and Engineering Symposium May 1968 The increasing complexity of multiprocessor computer systems with a high degree of parallelism within the computer system has created major internal communication problems. If each processing unit should be able to communicate with many other subsystems, the author recommends either a data exchange, or switching center, or parallel point-to-point wiring. The latter has the advantage of fast transfer and minimal data registers, but in a multiprocessor it results in a large number of cables. This paper discusses the state-of-the-art of internal multiplexing and multi-level coding schemes for reducing the number of lines in the system.

W1 E G Wagner On connecting modules together uniformly to form a modular computer IEEE Transactions on Computers December 1966 pp 864--872 This paper provides mathematical group theoretic precision to the idea of uniform bus structure in cellular computers.

W2 P W Ward A scheme for dynamic priority control in demand actuated multiplexing IEEE Computer Society Conference Boston September 1971 pp 51--52 This paper describes a priority conflict resolution method which is used in an I/O multiplexer system.

W3 R Watson Timesharing system design concepts Chapter 3---Communications McGraw-Hill 1970 pp 78--110 This chapter provides a summary of "communication" among memories, processors, IOP's, etc. The discussion is oriented toward example configurations. Subjects discussed are: (1) use of multiple memory modules, interleaving, and buffering to increase memory bandwidth; (2) connection of subsystems using direct connections, crossbar switches, multiplexed busses, etc.; and (3) the transmission medium. Items discussed under transmission medium are synchronous and asynchronous transmission, line types (simplex, half-duplex, and full-duplex), modulation, etc.

W4 D R Weller A loop communication system for I/O to a small multi-user computer IEEE Computer Society Conference Boston September 1971 pp 49--50 This paper describes a single-line non-dedicated bus with daisy-chained control for the DDP-516 computer. Message format and speed of operation are detailed.

W5 G P West R J Koerner Communications within a polymorphic intellectronic system Proceedings of Western Joint Computer Conference San Francisco May 3-5 1960 pp 225--230 This paper describes a crosspoint data exchange used in the RW-400 computer. The switch was mechanized using transfluxor cores.

W6 L P West Loop-transmission control structures IEEE Transactions on Communications June 1972 pp 531--539 This paper considers the problem of transmitting data on a communication loop. It discusses time slots, frame pulses, addressing techniques, and efficiency of utilization. It also discusses a number of ways for assigning time slots for utilization on the impact of slot size on loop utilization efficiency.

W7 M W Willard L J Horkan Maintaining bit integrity in time division transmission NAECON 1971 Record pp 240--247 This paper describes the tradeoffs involved in synchronizing high speed digital subsystems which are communicating over large distances. It considers clocking and buffering tradeoffs.

W8 D R Wulfinghoff Code activated switching---a solution to multiprocessing problems Computer Design April 1971 pp 67--71 The author points out that multiprocessor computer configurations have a large number of interconnections between elements causing considerable hardware and software complexity. He describes a technique whereby each program to be run is assigned a code, identifier, or signature; then when this program is activated the system resources it requires can be "lined-up" for use. He compares this scheme to that employed for telephone switching. Code activated switching is illustrated by two system block diagrams: a special purpose control computer and a general purpose time-shared computer.

Y1 B S Yolken Data bus---method for data acquisition and distribution within vehicles NAECON 1971 Record pp 248--253 This paper discusses a time division multiplexed bus, and considers bus control, bit synchronization, and technology tradeoffs.

Z1 R E Zimmerman The structure and organization of communication processors PhD Dissertation Electrical Engineering Department University of Michigan September 1971 This dissertation describes a multi-bus computer used as a terminal processor. It has a pair of instruction busses which start and then signal completion of processes performed in functional units or subsystems. The machine has three data busses: a memory bus which serves as the primary system communication bus, a flag address bus, and a flag data bus. All busses are eight bits wide and the three data busses are bidirectional.

Z2 R J Zingg Structure and organization of a pattern processor for hand-printed character recognition PhD Dissertation Iowa State University Ames Iowa 1968 This dissertation describes a bus-oriented special purpose computer designed for research in character recognition. The machine contains a control bus, a scratchpad memory bus, and three data busses. Each register that can be reached by a data bus has two control flip-flops associated with it and these determine to which data bus it is to be connected. These connections are controlled by a hardware command. The contents of several registers can be placed on one data bus to yield a bit-by-bit logical inclusive OR. Also, the contents of one data bus can be transferred to several registers and the contents of all three busses transferred in parallel under program command. This processor is a rather interesting example of a five bus processor.