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Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis

Published: 07 April 2009 Publication History

Abstract

Hardware module reuse is a standard solution to the problems of increasing complexity of chip architectures and pressure to reduce time to market. In the absence of a single module interface standard, predesigned modules for “plug-and-play” usually require a converter between incompatible interface protocols. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the HDL implementation level or grossly simplify the structure of the protocols considered. This work presents a state-machine-based formalism for modeling bus-based communication protocols and a notion of protocol compatibility and of correct conversion between incompatible protocols. This formalism is used to derive algorithms for checking protocol compatibility and for provably correct, automatic converter synthesis. Experiments with automatic converter synthesis between different configurations of widely used commercial bus protocols, such as AMBA AHB, ASB APB, and the Open Core Protocol (OCP) are discussed. The work here is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modeling of protocol characteristics that is also close to HDL.

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 14, Issue 2
March 2009
384 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/1497561
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 07 April 2009
Accepted: 01 October 2008
Revised: 01 September 2008
Received: 01 May 2008
Published in TODAES Volume 14, Issue 2

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Author Tags

  1. System-on-chip
  2. automatic design
  3. converter synthesis
  4. protocol compatibility

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  • (2016)Formal Design Flows for Embedded IoT HardwareComponents and Services for IoT Platforms10.1007/978-3-319-42304-3_2(27-55)Online publication date: 24-Sep-2016
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