Xrysovalantis Kavousianos
Abstract
Gating of the outputs of a portion of the scan cells (partial gating) has been recently proposed as a method for reducing the dynamic power dissipation during scan-based testing. We present a new systematic method for selecting, under area and performance design constraints, the most suitable for gating subset of scan cells as well as the proper gating value for each one of them, aiming at the reduction of the average switching activity during testing. We show that the proposed method outperforms the corresponding already known methods, with respect to average dynamic power dissipation reduction.
- Bardell, P. H., McAnney, W. H., and Savir, J. 1987. Built-In Test for VLSI: Pseudorandom Techniques. John Willey and Sons, 193--202. Google Scholar
Digital Library
- Bhunia, S., Mahmoodi, H., Ghosh, D., Mukhopadhyay, S., and Roy, K. 2005. Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13, 3, 384--395. Google ScholarDigital Library
- Bonhomme, Y., Girard, P., Landrault, C., and Pravossoudovitch, S. 2002. Power driven chaining of flip-flops in scan architectures. In Proceedings of International Test Conference, 796--803. Google ScholarDigital Library
- Bonhomme, Y., Girard, P., Guiller, L., Landrault, C., Pravossoudovitch, S., and Virazel, A. 2006. A gated clock scheme for low power testing of logic cores. J. Electron. Test.: Theor. Appl. 22, 89--99. Google ScholarDigital Library
- Butler, K., Saxena, J., Fryars, T., Hetherington, G., Jain, A., and Lewis, J. 2004. Minimizing power consumption in scan testing: Pattern generation and DFT Techniques. In Proceedings of the International Test Conference, 355--364. Google ScholarDigital Library
- Dabholkar, V. and Chakravarty, S. 1994. Two techniques for minimizing power dissipation in scan circuits during test application. In Proceedings of IEEE Asian Test Symposium. 324--329.Google Scholar
- Dabholkar, V., Chakravarty, S., Pomeranz, I., and Reddy, S. 1998. Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput. Aid.-Des. Integr. Circ. Syst. 17, 12, 1325--1333. Google ScholarDigital Library
- Elshoukry, M., Tehranipoor, M., and Ravikumar, C. 2007. A critical-path-aware partial gating approach for test power reduction. ACM Trans. Des. Automat. Electron. Syst. 12, 2, 242--247. Google ScholarDigital Library
- Gerstendorfer, S. and Wunderlich, H. 2000. Minimized power consumption for scan-based BIST. J. Electron. Test.: Theor. Appl. 16, 3, 203--212. Google ScholarDigital Library
- Girard, P., Landrault, C., Pravossoudovitch, S., and Severac, D. 1998. Reducing power consumption during test application by test vector ordering. In Proceedings of the IEEE International Symposium on Circuits and System. 296--299.Google Scholar
- Girard, P. 2002. Survey of low-power testing of VLSI Circuits, IEEE Des. Test Comput. 82--92. Google ScholarDigital Library
- Kavousianos, X., Kalligeros, E., and Nikolos, D. 2007. Multilevel Huffman Coding: An efficient test-data compression method for IP cores. IEEE Trans. Comput. Aid.-Des. Integr. Circ. Syst. 26, 6, 1070--1083. Google ScholarDigital Library
- Parimi, N. and Sun, X. 2004. Toggle-masking for test-per-scan VLSI circuits. In Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 332--338. Google ScholarDigital Library
- Remersaro, S., Lin, X., Zhang, Z., Reddy, S., Pomeranz, I., and Rajski, J. 2006. Preferred fill: A scalable method to reduce capture power for scan based designs. In Proceedings of the International Test Conference. 32.2.1--32.2.10.Google Scholar
- Sankaralingam, R. and Touba, N. 2002. Inserting test points to control peak power during scan testing. In Proceedings of the 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 138--146. Google ScholarDigital Library
- Saxena, J., Butler, K., and Whetsel, L. 2001. An analysis of power reduction techniques in scan testing. In Proceedings of the International Test Conference. 670--677. Google ScholarDigital Library
- Sharifi, S., Jaffari, J., Hosseinabady, M., Afzali-Kusha, A., and Navabi, Z. 2005. Simultaneous reduction of dynamic and static power in scan structures. In Proceedings of the Design Automation and Test in Europe Conference. 846--851. Google ScholarDigital Library
- Sinanoglu, O. and Orailoglu, A. 2002. Scan power reduction through test data transition frequency analysis. In Proceedings of the International Test Conference. 844--850. Google ScholarDigital Library
- Wang, S. and Gupta, S. 2002. An automatic test pattern generator for minimizing switching activity during scan testing activity. IEEE Trans. Comput. Aid.-Des. Integr. Circ. Syst. 21, 8, 954--968. Google ScholarDigital Library
- Whetsel, L. 2000. Adapting scan architectures for low power operation. In Proceedings of the International Test Conference. 863--872. Google ScholarDigital Library
- Zhang, X. and Roy, K. 2000. Power reduction in test-per-scan BIST. In Proceedings of the 6th International OnLine Test Workshop. 133--138. Google ScholarDigital Library
Index Terms
- Efficient partial scan cell gating for low-power scan-based testing
Recommendations
A critical-path-aware partial gating approach for test power reduction
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to block transitions propagating from the outputs of scan cells through ...
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
This article presents several scan-cell reordering techniques to reduce the signal transitions during the test mode while preserving the don’t-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the ...
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell
Shrinking technologies to deep sub-microns has raised demands for high quality testing. However, excessive power during test application time serves as limiting factors for reliability in testing. To address these issues, we have proposed Integrated Low ...
Comments