David J. Bastyr
ABSTRACT
When designing an interprocessor communications discipline, the problem of controlling data transaction on the interprocessor communications links has been traditionally solved by designating one processor as the central controller (the Master). All other processors are designated Slave processors which cannot utilize the interprocessor links unless requested by the master processor.
An alternative approach is to allow the interprocessor link to determine the Master/Slave relationship based on which processor has requested and received control of the link. An interprocessor link is in the neutral state (neither processor is Master or Salve) until a request for control is received from one of the processors. This processor is notified via hardware interrupt that it is the Master processor. Conversely, the other processor is notified that it is the Slave processor and is also informed of the nature of the pending transaction. When the interprocessor transaction has been completed, the Master processor releases control of the interprocessor link. The Slave processor is then notified that the interprocessor link is neutral again. Either processor can now request control of the interprocessor link.
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