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RADCAP: an operational parallel processing facility

Authors:

James D. Feldman,

Louis C. FulmerAuthors Info & Claims

AFIPS '74: Proceedings of the May 6-10, 1974, national computer conference and exposition

Pages 7 - 15

https://doi.org/10.1145/1500175.1500178

Published: 06 May 1974 Publication History

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Abstract

An overview is presented of RADCAP, the operational associative array processor (AP) facility installed at Rome Air Development Center (RADC). Basically, this facility consists of a Goodyear Aerospace STARAN associative array (parallel) processor and various peripheral devices, all interfaced with a Honeywell Information Systems (HIS) 645 sequential computer, which runs under the Multics timeshared operating system. The RADCAP hardware and software are described only briefly here since they are detailed in companion papers presented at this conference. The latter part of this paper dwells on the objectives of the RADCAP facility and plans for its use.

The STARAN associative parallel processor is a processor based on an associative or content addressable memory and a related ensemble of bit serial processing elements. STARAN is considered to be the first practical associative processor ever produced. This claim of practicality is based on the fact that the design concept for the associative memory of STARAN allows the use of the same high-volume, standard, large-scale integrated (LSI) circuit memory devices that are in widespread use by the computer industry. In fact, every electronic component used in the STARAN associative parallel processor is-available from your local components distributor. The significance of this fact is that now, for the first time, associative processors enjoy the same cost per bit of storage as does the conventional computer.

References

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Batcher, K. E., STARAN Parallel Processor System Hardware, GER-15996, Akron, Ohio, Goodyear Aerospace Corporation, 19 November 1973.

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Davis, E. W., STARAN Parallel Processor System Software, GER-15997, Akron, Ohio, Goodyear Aerospace Corporation, Akron, Ohio, 19 November 1973.

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Chisvin LDuckworth R(1992)Content-Addressable and Associative MemoryAdvances in Computers Volume 3410.1016/S0065-2458(08)60326-5(159-235)Online publication date: 1992
https://doi.org/10.1016/S0065-2458(08)60326-5
Lea R(1975)Information Processing with an Associative Parallel ProcessorComputer10.1109/C-M.1975.2188008:11(25-32)Online publication date: 1-Nov-1975
https://dl.acm.org/doi/10.1109/C-M.1975.218800
Batcher K(1974)STARAN parallel processor system hardwareProceedings of the May 6-10, 1974, national computer conference and exposition10.1145/1500175.1500260(405-410)Online publication date: 6-May-1974
https://dl.acm.org/doi/10.1145/1500175.1500260

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AFIPS '74: Proceedings of the May 6-10, 1974, national computer conference and exposition

May 1974

1083 pages

ISBN:9781450379205

DOI:10.1145/1500175

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 06 May 1974

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Chisvin LDuckworth R(1992)Content-Addressable and Associative MemoryAdvances in Computers Volume 3410.1016/S0065-2458(08)60326-5(159-235)Online publication date: 1992
https://doi.org/10.1016/S0065-2458(08)60326-5
Lea R(1975)Information Processing with an Associative Parallel ProcessorComputer10.1109/C-M.1975.2188008:11(25-32)Online publication date: 1-Nov-1975
https://dl.acm.org/doi/10.1109/C-M.1975.218800
Batcher K(1974)STARAN parallel processor system hardwareProceedings of the May 6-10, 1974, national computer conference and exposition10.1145/1500175.1500260(405-410)Online publication date: 6-May-1974
https://dl.acm.org/doi/10.1145/1500175.1500260

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WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory

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Mellow writes: extending lifetime in resistive memories through selective slow write backs

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WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory

A Novel Memory Block Management Scheme for PCM Using WOM-Code

Mellow writes: extending lifetime in resistive memories through selective slow write backs

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