Definition of architectures capable of fault tolerance and reconfiguration, suitable for very large scale integration (VLSI) implementation, is an important problem with regard to both production yield and run-time availability of VLSI devices. The case considered in the present paper concerns regular arrays of processing elements, such as the ones found in signal processing and other dedicated structures. It is proposed to achieve fault tolerance through the introduction of spare elements and reconfiguration algorithms implemented by suitable dedicated circuits and signals. A number of reconfigurable structures are presented, with different numbers and patterns of spare elements and with varying degrees of fault tolerance. Underlying fault assumptions are discussed and performances are analyzed; while architectures examined in detail consist of combinatorial elements with fairly simple interconnection schemes, extension to a wider class of structures is also considered. Implementation of diagnosis and reconfiguration is carried out at gate level: the resulting complexity is seen to be minor, as compared to the overall architecture complexity.