Stephen Friedman
Brian Van Essen
ABSTRACT
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FPGA style placement and pipelined routing algorithms with novel mechanisms for integrating and adapting the algorithms to CGRAs. We introduce a latency padding technique that provides feedback from the placer to the scheduler to meet the constraints of a fixed frequency device with configurable interconnect. Using a new dynamic clustering method during placement, we achieved a 1.3x improvement in throughput of mapped designs. Finally, we introduce an enhancement to the PathFinder algorithm for targeting architectures with a mix of dynamically multiplexed and statically configurable interconnects. The enhanced algorithm is able to successfully share statically configured interconnect in a time-multiplexed way, achieving an average channel width reduction of .5x compared to non-shared static interconnect.
- Electric VLSI Design System. Sun Microsystems and Static Free Software. http://www.staticfreesoft.com/.Google Scholar
- Mosaic Research Group. http://www.cs.washington.edu/research/lis/mosaic/.Google Scholar
- V. Betz and J. Rose. VPR: A New Packing, Placement and Routing Tool for FPGA Research. In International Workshop on Field-Programmable Logic and Applications, 1997. Google ScholarDigital Library
- A. Carroll and C. Ebeling. Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. In International Conference on Field-Programmable Logic and Applications, 2006.Google Scholar
- A. Carroll, S. Friedman, B. Van Essen, A. Wood, B. Ylvisaker, C. Ebeling, and S. Hauck. Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency. Technical report, Department of Energy NA-22 University Information Technical Interchange Review Meeting, 2007.Google Scholar
- C. Ebeling, D. C. Cronquist, and P. Franklin. RaPiD -- Reconfigurable Pipelined Datapath. In International Workshop on Field-Programmable Logic and Applications, pages 126--135, 1996. Google ScholarDigital Library
- K. Eguro and S. Hauck. Armada: Timing-driven Pipeline-aware Routing for FPGAs. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 169--178, 2006. Google ScholarDigital Library
- S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by Simulated Annealing. Science, 220:671--680, 1983.Google Scholar
- J.-e. Lee, K. Choi, and N. Dutt. Compilation Approach for Coarse-grained Reconfigurable Architectures. IEEE Design & Test of Computers, 20(1):26--33, 2003. Google ScholarDigital Library
- S. Li and C. Ebeling. QuickRoute: A Fast Routing Algorithm for Pipelined Architectures. In IEEE International Conference on Field-Programmable Technology, pages 73--80, 2004.Google Scholar
- L. McMurchie and C. Ebeling. PathFinder: A Negotiation-based Performance-driven Router for FPGAs. In ACM International Symposium on Field-Programmable Gate Arrays, pages 111--117, 1995. Google ScholarDigital Library
- B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. DRESC: A Retargetable Compiler for Coarse-grained Reconfigurable Architectures. In IEEE International Conference on Field-Programmable Technology, pages 166--173, 2002.Google Scholar
- B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In International Conference on Field-Programmable Logic and Applications, volume 2778, pages 61--70, 2003.Google Scholar
- E. Mirsky and A. DeHon. MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In IEEE Symposium on Field-Programmable Custom Computing Machines, pages 157--166, 1996.Google ScholarCross Ref
- M. Mishra and S. C. Goldstein. Virtualization on the Tartan Reconfigurable Architecture. In International Conference on Field-Programmable Logic and Applications, pages 323--330, 2007.Google Scholar
- B. R. Rau. Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops. In International Symposium on Microarchitecture, pages 63--74, 1994 Google ScholarDigital Library
- A. Sharma, S. Hauck, and C. Ebeling. Architecture-adaptive Routability-driven Placement for FPGAs. In International Conference on Field-Programmable Logic and Applications, pages 427--432, 2005.Google Scholar
- H. Singh, M.-H. Lee, G. Lu, F. Kurdahi, N. Bagherzadeh, and E. Chaves Filho. MorphoSys: An Integrated Reconfigurable System for Data-parallel and Computation-Intensive Applications. IEEE Transactions on Computers, 49(5):465--481, 2000. Google ScholarDigital Library
- W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. DeHon. HSRA: High-speed, Hierarchical Synchronous Reconfigurable Array. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 125--134, 1999. Google ScholarDigital Library
- S. J. Wilton. Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory. PhD thesis, University of Toronto, 1997. Google ScholarDigital Library
Index Terms
- SPR: an architecture-adaptive CGRA mapping tool
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