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HW/SW methodologies for synchronization in FPGA multiprocessors

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Donatella SciutoAuthors Info & Claims

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Pages 265 - 268

https://doi.org/10.1145/1508128.1508174

Published: 22 February 2009 Publication History

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Abstract

odern Field Programmable Gate Arrays (FPGA) can be programmed with multiple soft-core processors. These solutions can be used for MultiProcessor Systems-on-Chip (MPSoCs) prototyping or even for final implementation. Nevertheless, efficient synchronization is required to guarantee performance in multiprocessing environments with the simple cores that do not support atomic instructions and are normally used in the standard FPGA toolchains. In this paper, we introduce two hardware synchronization modules for Xilinx MicroBlaze systems, with local polling or queuing mechanisms for locks and barriers, and present a comparison of these solutions to alternative designs.

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Lu CPilato CBasu K(2024)QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339169943:10(3015-3026)Online publication date: 1-Oct-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3391699
Hansen HMaroun EKristensen AMarquart JSchoeberl M(2017)A shared scratchpad memory with synchronization support2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2017.8124992(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/NORCHIP.2017.8124992
Mirian VChow P(2015)Exploring pipe implementations using an OpenCL framework for FPGAs2015 International Conference on Field Programmable Technology (FPT)10.1109/FPT.2015.7393135(112-119)Online publication date: Dec-2015
https://doi.org/10.1109/FPT.2015.7393135
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Index Terms

HW/SW methodologies for synchronization in FPGA multiprocessors
1. Computer systems organization
  1. Architectures
    1. Distributed architectures

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Published In

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

February 2009

302 pages

ISBN:9781605584102

DOI:10.1145/1508128

General Chair:
Paul Chow
University of Toronto, Canada
,
Program Chair:
Peter Cheung
Imperial College London, UK

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Association for Computing Machinery

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Published: 22 February 2009

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FPGA '09: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2009

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Lu CPilato CBasu K(2024)QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339169943:10(3015-3026)Online publication date: 1-Oct-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3391699
Hansen HMaroun EKristensen AMarquart JSchoeberl M(2017)A shared scratchpad memory with synchronization support2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2017.8124992(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/NORCHIP.2017.8124992
Mirian VChow P(2015)Exploring pipe implementations using an OpenCL framework for FPGAs2015 International Conference on Field Programmable Technology (FPT)10.1109/FPT.2015.7393135(112-119)Online publication date: Dec-2015
https://doi.org/10.1109/FPT.2015.7393135
Rutgers JBekooij MSmit G(2012)An efficient asymmetric distributed lock for embedded multiprocessor systems2012 International Conference on Embedded Computer Systems (SAMOS)10.1109/SAMOS.2012.6404172(176-182)Online publication date: Jul-2012
https://doi.org/10.1109/SAMOS.2012.6404172
Marzi HYang Y(2012)Microkernel based real-time embedded operating systems efficiency improvement2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE.2012.6335029(1-4)Online publication date: Apr-2012
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Pusceddu MCeccolini STumeo APalermo GSciuto D(2011)Emulating transactional memory on FPGA multiprocessorsProceedings of the 24th international conference on Architecture of computing systems10.5555/1966221.1966231(74-85)Online publication date: 24-Feb-2011
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Stoif CSchoeberl MLiccardi BHaase J(2011)Hardware synchronization for embedded multi-core processors2011 IEEE International Symposium of Circuits and Systems (ISCAS)10.1109/ISCAS.2011.5938126(2557-2560)Online publication date: May-2011
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Shen HQiu Q(2011)An FPGA-Based Distributed Computing System with Power and Thermal Management Capabilities2011 Proceedings of 20th International Conference on Computer Communications and Networks (ICCCN)10.1109/ICCCN.2011.6005802(1-6)Online publication date: Jul-2011
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Pusceddu MCeccolini STumeo APalermo GSciuto D(2011)Emulating Transactional Memory on FPGA MultiprocessorsArchitecture of Computing Systems - ARCS 201110.1007/978-3-642-19137-4_7(74-85)Online publication date: 2011
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Dorta TJiménez JMartín JBidarte UAstarloa A(2010)Reconfigurable multiprocessor systemsInternational Journal of Reconfigurable Computing10.1155/2010/5702792010(1-10)Online publication date: 1-Feb-2010
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