ABSTRACT
Future generation multiprocessor system on chip (MPSOC) will be based on hundreds of processors connected through network on chips. One of the challenges is to tackle the design productivity required to reach this goal. We propose a NOC based small scale multiprocessor IP (SSM IP) as a building block for large scale multiprocessor. The architecture of the small scale multiprocessor is based on a 2x2 mesh with 3 Xilinx Microblaze processors and 2 SRAM on chip memories per switch. The network on chip topology is mesh for its scalability properties and easy extensibility. A clustered design has been preferred over a full mesh in order to fully exploit the data locality processing of image and multimedia applications. The implementation of the small scale multiprocessor has been realized by targeting the largest Xilinx Virtex-4 FPGA chip the FX140. Design has been realized using the Xilinx tools (EDK, ISE) with the Xilinx library of IPs. The objective of the implementation was to design a multiprocessor of sufficient scale to be significant while leaving some chip area and resources for design space exploration. Images can be distributed equally among the shared memories of each cluster so that processors belonging to a cluster can operate on the image portion associated to a cluster. Architectural variations among 4 selected architectures demonstrate the area saving and performance potential of soft IP. In addition reasonable synthesis, place and route execution time and achieved target frequencies justify the design effort.
- ITRS http://www.itrs.net/Google Scholar
- A.A.Jerraya and W.Wolf, "Multiprocessor Systems-on-Chips", Morgan Kaufman Pub., 2004.Google Scholar
- Mouhoub, R.B.; Hammami, O.;Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution PDPS 2006, 25-29 April 2006 Page(s):8 pp. Google ScholarDigital Library
- S.Hauck and A.DeHon, "Reconfigurable Computing The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann 2007. Google ScholarDigital Library
- Li, X.; Hammami, O.;, NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis, Industrial Embedded Systems, 2006. IES '06. International Symposium on 18-20 Oct. 2006 Page(s):1--4Google ScholarCross Ref
- CHIPit Platinum Edition -- ASIC Emulation and Rapid Prototyping System == v.2.0., 2004, ProDesign www.uchipit.comGoogle Scholar
- R. Ben Mouhoub and O. Hammami, "MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution," EURASIP Journal on Embedded Systems, vol. 2006, Article ID 54074, 14 pages, 2006. Google ScholarDigital Library
- O.Hammami, "Heterogeneous Multiprocessor on chip Compiler, Architecture, PLace and Route Design Space Exploration", in IEEE MELECON, May 5-7, 2008, Ajaccio, FranceGoogle ScholarCross Ref
- N. Genko, D. Atienza, G. De Micheli, J. M. Mendias, R. Hermida, F. Catthoor, A Complete Network-On-Chip Emulation Framework, Proceedings of the conference on Design, Automation and Test in Europe Volume 1 DATE '05, March 2005 Google ScholarDigital Library
- Nava, M.D.; Blouet, P.; Teninge, P.; Coppola, M.; Ben-Ismail, T.; Picchiottino, S.; Wilson, R.; An open platform for developing multiprocessor SoCs, Computer, Volume 38, Issue 7, July 2005 Page(s):60--67 Google ScholarDigital Library
- E.S. Chung, E. Nurvitadhi, J.C. Hoe, B.Falsafi, K.Mai Virtualized Full-System Emulation of Multiprocessors using FPGAs, 2nd Workshop on Architectural Research Prototyping WARP-2007Google Scholar
- K. Asonvic, RAMP: Research Accelerator for Multiprocessors, 2nd Workshop on Architectural Research Prototyping, WARP-2006Google Scholar
- Arteris S.A. http://www.arteris.comGoogle Scholar
- NoC Solution 1.10, NoC Compiler user's Guide, o918v2rs4, Dec. 2008, Arteris www.arteris.comGoogle Scholar
- Danube 1.10 -- Packet Transport Units Technical reference -- 04277v3rs6 -- March 2008, Arteris. www.arteris.comGoogle Scholar
- Xilinx. Embedded system tools guide. Available on: http://www.xilinx.com/ise/embedded/edk docs.htm.Google Scholar
- Xilinx. Xilinx fast simplex link ip. Available on: http://www.xilinx.com/bvdocs/ipcenter/data sheet/FSL V20.pdf.Google Scholar
- Xilinx. Xilinx microblaze soft core processor. Available on: http://www.xilinx.com/ise/embedded/mb ref guide.pdf.Google Scholar
- Alpha-Data. ADM-XRC-4 PCI mezzanine card. Available on: http://www.alpha-data.com/.Google Scholar
- EVE TEAM Zebu-UF Emulation platform. www.eve-team.comGoogle Scholar
Index Terms
- Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation
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