MEDEA

CPU speeds have increased faster than the rate of improvement in memory access latencies in the recent past. As a result, with programs that suffer excessive cache misses, the CPU will increasingly be stalled waiting for the memory system to provide the ...

Recently, chip multiprocessors (CMPs) that can simultaneously execute multiple workloads using multiple cores have become a key to achieve high-performance processing. To improve CMP performance, various shared resource management mechanisms have been ...

The considerable gap between processor and DRAM speed and the power losses in the cache hierarchy calls for more efficient approaches. Broadly speaking, cache-hierarchy efficiency can be increased either by improving cache management or by reducing the ...

This paper discusses the design of a chip multi vector processor (CMVP), especially examining the effects of an on-chip cache when the off-chip memory bandwidth is limited. As chip multiprocessors (CMPs) have become the mainstream in commodity scalar ...

Power dissipation becomes an important issue in modern microprocessors such as chip multiprocessors (CMPs). Especially as the process technology advances below 90nm, the leakage power consumption becomes dominant in the total power dissipation, thus ...

For precise timing analysis of hard-real applications a predictable memory system is of particular importance. Caches have a great impact on performance, but at the cost of reduced timing predictability. Conventional scratchpads, i.e. statically managed ...

As database management systems gain importance in our everyday life, it is essential to have efficient implementations of important database operations such as the hash join. Improvements in processor architectures including simultaneous multithreaded ...

As mobile applications and devices become ubiquitous, consumer demands for performance, power efficiency, and connectivity are increasing. The software framework existing on mobile internet devices is a complex interaction of real-time tasks, non-real-...

Transactional Memory (TM) is a promising new technology that makes it possible to ease writing multi-threaded applications. Many different TM implementations exist, unfortunately most of those TM systems are currently evaluated by using workloads that ...

Transactional Memory is a promising parallel programming model that addresses the programmability issues of lock-based applications using mechanisms that are transparent to developers. Hardware Transactional Memory (HTM) implements these mechanisms in ...

With the advent of multicore architectures, especially with the heterogeneous ones, both computational and memory top performance are difficult to obtain using traditional programming models. Usually, programmers have to fully reorganize the code and ...