skip to main content
10.1145/1509084.1509090acmotherconferencesArticle/Chapter ViewAbstractPublication PagesmedeaConference Proceedingsconference-collections
research-article

Predictable dynamic instruction scratchpad for simultaneous multithreaded processors

Published: 26 October 2008 Publication History

Abstract

For precise timing analysis of hard-real applications a predictable memory system is of particular importance. Caches have a great impact on performance, but at the cost of reduced timing predictability. Conventional scratchpads, i.e. statically managed on-chip memories, provide predictable memory accesses, but they are usually badly utilized. Better memory utilization is allowed by dynamically managed scratchpads that are designed for predictability. In this paper we propose a function scratchpad that is dynamically managed in hardware and provides a predictable timing behavior. The function scratchpad exploits a simultaneous multithreaded architecture to increase the pipeline and memory bandwidth utilization while preserving predictability.

References

[1]
T. Aa, M. Jayapala, F. Barat, G. Deconinck, R. Lauwereins, H. Corporaal, and F. Catthoor. Instruction Buffering Exploration for Low Energy Embedded Processors. Journal of Embedded Computing, 1(3):341--351, 2005.
[2]
B. Akesson, K. Goossens, and M. Ringhofer. Predator: a Predictable SDRAM Memory Controller. Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pages 251--256, 2007.
[3]
R. Banakar, S. Steinke, B. Lee, M. Balakrishnan, and P. Marwedel. Scratchpad Memory: Design Alternative for Cache On-Chip Memory in Embedded Systems. Proceedings of the tenth international symposium on Hardware/software codesign, pages 73--78, 2002.
[4]
J. Barre, C. Rochange, and P. Sainrat. A Predictable Simultaneous Multithreading Scheme for Hard Real-Time. In International Conference on Architecture of Computing Systems, number 4934 in LNCS, pages 161--172, Feb 2008.
[5]
H. Falk, S. Plazar, and H. Theiling. Compile-Time Decided Instruction Cache Locking Using Worst-Case Execution Paths. Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pages 143--148, 2007.
[6]
HighTec EDV-Systeme GmbH. Website. http://www.hightec-rt.com/.
[7]
Infineon Technologies AG. TriCore 1 User's Manual, Jan 2008. V1.3.8.
[8]
A. Janapsatya, A. Ignjatovic, and S. Parameswaran. Exploiting Statistical Information for Implementation of Instruction Scratchpad Memory in Embedded System. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 14(8):816--829, 2006.
[9]
M. Kandemir, J. Ramanujam, M. Irwin, N. Vijaykrishnan, I. Kadayif, and A. Parikh. Dynamic Management of Scratch-Pad Memory Space. Design Automation Conference, 2001. Proceedings, pages 690--695, 2001.
[10]
R. Kirner and M. Schoeberl. Modeling the Function Cache for Worst-Case Execution Time Analysis. Proceedings of the 44th annual conference on Design automation, pages 471--476, 2007.
[11]
J. Mische, S. Uhrig, F. Kluge, and T. Ungerer. Exploiting Spare Resources of In-order SMT Processors Executing Hard Real-time Threads. In IEEE International Conference on Computer Design 2008 (ICCD 08), Lake Tahoe, Oct. 2008.
[12]
Mäalardalen Real-Time Research Center (MRTC). WCET Benchmark Suite. Website. http://www.mrtc.mdh.se/projects/wcet/benchmarks.html.
[13]
I. Puaut and C. Pais. Scratchpad Memories vs Locked Caches in Hard Real-Time Systems: a Quantitative Comparison. Proceedings of the conference on Design, automation and test in Europe, pages 1484--1489, 2007.
[14]
J. Reineke, D. Grund, C. Berg, and R. Wilhelm. Timing Predictability of Cache Replacement Policies. Real-Time Systems, 37(2):99--122, 2007.
[15]
M. Schoeberl. A Time Predictable Instruction Cache for a Java Processor. On the Move to Meaningful Internet Systems 2004: Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES 2004), 3292:371--382.
[16]
S. Steinke, N. Grunwald, L. Wehmeyer, R. Banakar, M. Balakrishnan, and P. Marwedel. Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. International Symposium on Systems Synthesis: Proceedings of the 15 th international symposium on System Synthesis, 2(04):213--218, 2002.
[17]
V. Suhendra, T. Mitra, A. Roychoudhury, and T. Chen. WCET Centric Data Allocation to Scratchpad Memory. RTSS'05: Proceedings of the 26th IEEE International Real-Time Systems Symposium.
[18]
S. Uhrig, S. Maier, and T. Ungerer. Toward a Processor Core for Real-Time Capable Autonomic Systems. IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2005, Athen, Greece, 2005.
[19]
L. Wehmeyer and P. Marwedel. Influence of Onchip Scratchpad Memories on WCET Prediction. Proceedings of the 4th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2004.
[20]
J. Whitham and N. Audsley. Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures. In Proc. RTAS, 2008.
[21]
R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenströom. The Worst-Case Execution-Time Problem --- Overview of Methods and Survey of Tools. Trans. on Embedded Computing Sys., 7(3):1--53, 2008.

Cited By

View all
  • (2017)Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2017.17(76-83)Online publication date: May-2017
  • (2014)WCET-Based Comparison of an Instruction Scratchpad and a Method CacheProceedings of the 2014 IEEE 17th International Symposium on Object/Component-Oriented Real-Time Distributed Computing10.1109/ISORC.2014.48(301-308)Online publication date: 10-Jun-2014
  • (2014)A Method Cache for PatmosProceedings of the 2014 IEEE 17th International Symposium on Object/Component-Oriented Real-Time Distributed Computing10.1109/ISORC.2014.47(100-108)Online publication date: 10-Jun-2014
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences
MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
October 2008
88 pages
ISBN:9781605582436
DOI:10.1145/1509084
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 October 2008

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Research-article

Conference

MEDEA '08

Acceptance Rates

Overall Acceptance Rate 6 of 9 submissions, 67%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 05 Mar 2025

Other Metrics

Citations

Cited By

View all
  • (2017)Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2017.17(76-83)Online publication date: May-2017
  • (2014)WCET-Based Comparison of an Instruction Scratchpad and a Method CacheProceedings of the 2014 IEEE 17th International Symposium on Object/Component-Oriented Real-Time Distributed Computing10.1109/ISORC.2014.48(301-308)Online publication date: 10-Jun-2014
  • (2014)A Method Cache for PatmosProceedings of the 2014 IEEE 17th International Symposium on Object/Component-Oriented Real-Time Distributed Computing10.1109/ISORC.2014.47(100-108)Online publication date: 10-Jun-2014
  • (2014)BibliographyTime‐Predictable Architectures10.1002/9781118790229.biblio(163-178)Online publication date: 17-Jan-2014
  • (2013)A hard real-time capable multi-core SMT processorACM Transactions on Embedded Computing Systems10.1145/2442116.244212912:3(1-26)Online publication date: 8-Apr-2013
  • (2012)An instruction scratchpad memory allocation for the precision timed architectureProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492874(659-664)Online publication date: 12-Mar-2012
  • (2012)Is time predictability quantifiable?2012 International Conference on Embedded Computer Systems (SAMOS)10.1109/SAMOS.2012.6404196(333-338)Online publication date: Jul-2012
  • (2012)Exploiting SPM-aware Scheduling on EPIC architectures for high-performance real-time systems2012 IEEE Conference on High Performance Extreme Computing10.1109/HPEC.2012.6408658(1-2)Online publication date: Sep-2012
  • (2012)Impact of Instruction Cache and Different Instruction Scratchpads on the WCET EstimateProceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems10.1109/HPCC.2012.211(1442-1449)Online publication date: 25-Jun-2012
  • (2012)Replacement Policies for a Function-Based Instruction MemoryProceedings of the 2012 24th Euromicro Conference on Real-Time Systems10.1109/ECRTS.2012.22(112-121)Online publication date: 11-Jul-2012
  • Show More Cited By

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media