research-article

Redundant via insertion with wire bending

Authors:

Shing-Tung Lin,

Ting-Chi WangAuthors Info & Claims

ISPD '09: Proceedings of the 2009 international symposium on Physical design

Pages 123 - 130

https://doi.org/10.1145/1514932.1514960

Published: 29 March 2009 Publication History

Abstract

Redundant via insertion is highly recommended for improving chip yield and reliability. In this paper, we study the problem of double via insertion with wire bending (DVI/WB) in a post-routing stage, where a single via can have at most one redundant via inserted next to it. Aside from this, we are allowed to bend existing signal wires for enhancing the insertion rate of double vias. The goal of DVI/WB is to primarily insert as many double vias as possible and to minimize the amount of layout perturbation as the secondary objective. We formulate the DVI/WB problem as that of finding a minimum-weight maximum independent set (mWMIS) on an enhanced conflict graph. We propose algorithms to perform wire bending and to construct the enhanced conflict graph from a given design. Moreover, we also propose a zero-one integer linear program (0-1 ILP) based approach to solve mWMIS. Experimental results show that our approach can improve the insertion rate by up to 5.58% at the expense of up to 0.37% wirelengh increase when compared with a state-of-the-art double via insertion method that does not consider wire bending.

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Cited By

Ding YChu CMak W(2018)Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability ConsiderationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271266037:3(657-668)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2712660
Xu XLin YLi MOu JCline BPan D(2017)Redundant Local-Loop Insertion for Unidirectional RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265181136:7(1113-1125)Online publication date: 1-Jul-2017
https://dl.acm.org/doi/10.1109/TCAD.2017.2651811
Ding YChu CMak W(2016)Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability considerationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898088(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898088
Show More Cited By

Index Terms

Redundant via insertion with wire bending
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

ISPD '09: Proceedings of the 2009 international symposium on Physical design

March 2009

208 pages

ISBN:9781605584492

DOI:10.1145/1514932

General Chair:
Gi-Joon Nam
IBM Research
,
Program Chair:
Prashant Saxena
Synopsys

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 29 March 2009

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March 29 - April 1, 2009

California, San Diego, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Ding YChu CMak W(2018)Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability ConsiderationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271266037:3(657-668)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2712660
Xu XLin YLi MOu JCline BPan D(2017)Redundant Local-Loop Insertion for Unidirectional RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265181136:7(1113-1125)Online publication date: 1-Jul-2017
https://dl.acm.org/doi/10.1109/TCAD.2017.2651811
Ding YChu CMak W(2016)Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability considerationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898088(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898088
Fang SHong YLu YMarculescu DLiu F(2015)Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-AssemblyProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840877(410-417)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840877
Lin CLin YSu GLi YLin Y(2010)Dead via minimization by simultaneous routing and redundant via insertionProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899875(657-662)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899875
Lin CYen-Hung Lin Guan-Chan Su Li Y(2010)Dead Via Minimization by Simultaneous Routing and Redundant Via Insertion2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419806(657-662)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419806

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