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Selective shielding technique to eliminate crosstalk transitions

Published: 04 June 2009 Publication History

Abstract

With CMOS process technology scaling to deep submicron level, propagation delay across long on-chip buses is becoming one of the main performance limiting factors in high-performance designs. Propagation delay is very significant when adjacent wires are transitioning in opposite direction as compared to transitioning in the same direction. As opposite transitions on adjacent wires (called as crosstalk transitions) have significant impact on propagation delay, several bus encoding techniques have been proposed in literature to eliminate such transitions.
We propose selective shielding technique to eliminate crosstalk transitions. We show that the selective shielding technique requires ⌈3n/2⌉ wires to encode a n-bit bus. SPICE simulations by considering 90nm technology nodes reveal that, for uniformly distributed random data, our technique achieves nearly 39% (21%) delay savings over 10mm-length uncoded 32-bit bus for pipelined (nonpipelined) data transmission at the cost of nearly 7% energy overhead.

References

[1]
Arunachalam, R., Acar, E., and Nassif, S. 2003. Optimal shielding/spacing metrics for low power design. In International of the Symposium on Very Large Scale Integration (ISVLSI). IEEE Computer Society Press, Los Alamitos, CA, 167--172.
[2]
Caignet, F., Delmas-Bendhia, S., and Sicard, E. 2001. The challenge of signal integrity in deep-submicrometer CMOS technology. Proc. IEEE 89, 4, 556--573.
[3]
Duan, C., Tirumala, A., and Khatri, S. 2001. Analysis and avoidance of crosstalk in on-chip buses. In Proceedings Hot Interconnects 9. IEEE Computer Society Press, Los Alamitos, CA, 133--138.
[4]
Kaul, H., Sylvester, D., and Blauuw, D. 2002. Active shielding: A new approach to shielding global wires. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI). ACM, New York, 112--117.
[5]
Khan, Z., Arslan, T., and Erdogan, A. 2004. A dual low power and crosstalk immune encoding scheme for system-on-chip buses. In Proceedings of the 14th International Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS). Lecture Notes in Computer Science. Springer-Verlag, Berlin, Germany, 585--592.
[6]
Li, L., Vijaykrishnan, N., Kandemir, M., and Irwin, M. 2004. A crosstalk aware interconnect with variable cycle transmission. In Proceedings of the Conference on Design Automation and Test in Europe (DATE). IEEE Computer Society Press, Los Alamitos, CA, 102--107.
[7]
Mutyam, M. 2007. Selective shielding: A crosstalk-free bus encoding technique. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). ACM, New York, 618--621.
[8]
Mutyam, M., Eze, M., Vijaykrishnan, N., and Xie, Y. 2006. Delay and energy efficient data transmission for on-chip buses. In Proceedings of the International Symposium on Very Large Scale Integration (ISVLSI). IEEE Computer Society, Los Alamitos, CA, 355--360.
[9]
Najeeb, K., Gupta, V., Kamakoti, V., and Mutyam, M. 2006. Delay and peak power minimization for on-chip buses using temporal redundancy. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI). ACM, New York, 119--122.
[10]
Pamunuwa, D., Zheng, L.-R., and Tenhunen, H. 2003. Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trand. VLSI 11, 224--243.
[11]
Patel, K. and Markov, I. 2003. Error-correction and crosstalk avoidance in dsm busses. In Proceedings of the International Workshop on System Level Interconnect Prediction. ACM, New York, 9--14.
[12]
Predictive technology model. http://www.eas.asu.edu/~ptm.
[13]
Rossi, D., van Dijk, V., Kleihorst, R., Nieuwland, A., and Metra, C. 2002. Coding scheme for low energy fault-tolerant bus. In Proceedings of the 8th International On-Line Testing Workshop (IOLTW). IEEE Computer Society Pewss, Los Alamitos, CA, 8--12.
[14]
Sotiriadis, P. and Chandrakasan, A. 2000. Low power bus coding techniques considering inter-wire capacitances. In Proceedings of the 22nd Custom Integrated Circuits Conference (CICC). IEEE Computer Society Press, Los Alamitos, CA, 507--510.
[15]
Sotiriadis, P. and Chandrakasan, A. 2001. Reducing bus delay in sub-micron technology using coding. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC). ACM, New York, 109--114.
[16]
Sotiriadis, P. and Chandrakasan, A. 2002. A bus energy model for deep submicron technology. IEEE Trans. VLSI 10, 3, 331--350.
[17]
Sridhara, S., Ahmed, A., and Shanbhag, N. 2004. Area and energy-efficient crosstalk avoidance codes for on-chip buses. In Proceedings of the International Conference on Computer Design (ICCD). IEEE Computer Society Press, Los Alamitos, CA, 12--17.
[18]
Sridhara, S. and Shanbhag, N. 2005. Coding for system-on-chip networks: a unified framework. IEEE Trans. VLSI 13, 6, 655--667.
[19]
Stan, M. and Burleson, W. 1994. Limited-weight codes for low power I/O. In Proceedings of the International Workshop on Low Power Design. IEEE Computer Society Press, Los Alamitos, CA, 209--214.
[20]
Subramanya, P., Manimeghalai, R., Kamakoti, V., and Mutyam, M. 2004. A bus encoding technique for power and cross-talk minimization. In Proceedings of the International Workshop on Low Power Design. IEEE Computer Society Press, Los Alamitos, CA, 443--448.
[21]
Sylvester, D. and Hu, C. 2001. Analytical modeling and characterization of deep-submicrometer interconnect. Proc. IEEE 89, 5, 634--664.
[22]
Tiehan, L., Henkel, J., Lekatsas, H., and Wolf, W. 2003. Enhancing signal integrity through a low overhead encoding scheme on address buses. In Proceedings of the Conference on Design Automation and Test in Europe (DATE). IEEE Computer Society Press, Los Alamitos, CA.
[23]
Victor, B. and Keutzer, K. 2001. Bus encoding to prevent crosstalk delay. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). ACM, New York, 57--63.
[24]
Yim, J. and Kung, C. 1999. Reducing cross-coupling among interconnect wires in deep-submicron datapath design. In Proceedings of the ACM/IEEE Design Automation Conference (DAC). ACM, New York, 485--490.

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  • (2022)Energy Reduction Method by Compiler OptimizationArtificial Intelligence and Security10.1007/978-3-031-06794-5_54(672-683)Online publication date: 15-Jul-2022
  • (2018)NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnectsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345392:3/4(177-186)Online publication date: 13-Dec-2018
  • (2012)Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip busesIET Computers & Digital Techniques10.1049/iet-cdt.2010.00606:2(114)Online publication date: 2012
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 14, Issue 3
May 2009
376 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/1529255
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 June 2009
Accepted: 01 February 2009
Revised: 01 June 2008
Received: 01 February 2008
Published in TODAES Volume 14, Issue 3

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Author Tags

  1. Crosstalk
  2. bus encoding
  3. power consumption
  4. switching activity

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Cited By

View all
  • (2022)Energy Reduction Method by Compiler OptimizationArtificial Intelligence and Security10.1007/978-3-031-06794-5_54(672-683)Online publication date: 15-Jul-2022
  • (2018)NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnectsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345392:3/4(177-186)Online publication date: 13-Dec-2018
  • (2012)Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip busesIET Computers & Digital Techniques10.1049/iet-cdt.2010.00606:2(114)Online publication date: 2012
  • (2010)Power reduction by register relabeling for crosstalk-toggling free instruction bus coding2010 International Computer Symposium (ICS2010)10.1109/COMPSYM.2010.5685429(676-681)Online publication date: Dec-2010

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