ABSTRACT
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Index Terms
- Design challenges in high performance three-dimensional circuits
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High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits
Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free ...
Timing constraints for high-speed counterflow-clocked pipelining
With the escalation of clock frequencies and the increasing ratio of wire-to gate-delays, clock skew is a major problem to be overcome in tomorrow's high-speed very large scale integration (VLSI) chips. Also, with an increasing number of stages ...
On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic
An on-line error-detectable high-speed multiplier is described. It is based on the multiplication algorithm which we have previously proposed. In the algorithm, the redundant binary representation each of whose digits is 0, 1, or 1 is used. The ...
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