Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices

Dynamic reconfiguration capabilities exploited by modern FPGA devices improve the flexibility and the reliability of embedded systems. The increasing complexity demands for a design-paradigm shift towards a communication-centric approach. Networks-on-Chip are a promising design paradigm for both homogeneous and heterogeneous systems in which communication is represented in a network-like manner, even if they cannot directly be applied to the dynamic reconfiguration scenario. While in literature there are different approaches to design communication infrastructures able to support the reconfiguration of its functionalities, what seems to be neglected is the definition of a complete design flow for a dynamic reconfigurable communication infrastructure able to adapt itself at runtime to the current working scenario. This paper proposes a design flow to automatically create a reconfigurable architecture that consists of a grid of homogeneous tiles that can be filled with either computational (master or slave cores with their network interfaces) or communication (switches) elements.