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Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

Published: 10 May 2009 Publication History

Abstract

In H.264/AVC based integer motion estimation engine, fixed architectures based on full pixel or direct sub-sampling pattern are widely used for HDTV application. However, these architectures suffer from either high complexity or quality loss problems. In this paper, an adaptive sub-sampling based reconfigurable architecture is given out. Firstly, by executing pixel difference analysis, the adaptive sub-sampling scheme which uses three hardware friendly patterns is applied on homogeneous macroblock (MB). Secondly, the related architecture introduces one more pipeline stage to build up configurable partial SAD values so that system performance is enhanced. Thirdly, a two-level pixel data organization scheme is proposed to solve data reuse and hardware utilization problems caused by adaptive algorithm. Moreover, one cross based SAD generation structure is introduced to achieve adaptive output results with less hardware cost. Experimental results show that, the proposed architecture can averagely save 61.71% clock cycles and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency is 208MHz under the TSMC 0.18um technology in worst case conditions(1.62V, 125 C).

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Cited By

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  • (2019)Towards optimal use of pel decimation to trade off quality for energyAnalog Integrated Circuits and Signal Processing10.1007/s10470-015-0575-285:1(107-128)Online publication date: 1-Jan-2019
  • (2012)Synthesis and comparison of low-power high-throughput architectures for SAD calculationAnalog Integrated Circuits and Signal Processing10.1007/s10470-012-9971-z73:3(873-884)Online publication date: 18-Oct-2012

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cover image ACM Conferences
GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI
May 2009
558 pages
ISBN:9781605585222
DOI:10.1145/1531542
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 10 May 2009

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Author Tags

  1. h.264
  2. reconfigurable architecture
  3. vlsi

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GLSVLSI '09
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GLSVLSI '09: Great Lakes Symposium on VLSI 2009
May 10 - 12, 2009
MA, Boston Area, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2019)Towards optimal use of pel decimation to trade off quality for energyAnalog Integrated Circuits and Signal Processing10.1007/s10470-015-0575-285:1(107-128)Online publication date: 1-Jan-2019
  • (2012)Synthesis and comparison of low-power high-throughput architectures for SAD calculationAnalog Integrated Circuits and Signal Processing10.1007/s10470-012-9971-z73:3(873-884)Online publication date: 18-Oct-2012

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