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New performance/power/area efficient, reliable full adder design

Published: 10 May 2009 Publication History

Abstract

Arithmetic circuits have always played one of the most important roles in the designs of processors, FPGAs, and the rapidly evolving domain of media processing architectures. The full adder cell forms the basic building block of majority of these arithmetic circuits. In this paper we describe a hybrid pseudo static full adder cell designed using Data Driven Dynamic Logic. Simulation results show the adder to out perform its competitors, both static as well as dynamic topologies in terms of performance, while maintaining relatively similar area and power characteristics. This paper presents a complete characterization of the popular adder cells in terms of delay, area, power, noise margin and reliability analysis for both super threshold and sub threshold operating regimes.

References

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Cited By

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  • (2013)Designing Dynamic Carry Skip Adders: Analysis and ComparisonCircuits, Systems, and Signal Processing10.1007/s00034-013-9688-y33:4(1019-1034)Online publication date: 31-Oct-2013
  • (2012)Undergraduate Curriculum Development for Digital Integrated Circuit DesignCreative Education10.4236/ce.2012.32612803:06(856-858)Online publication date: 2012
  • (2011)Highly reliable and low-power full adder cell2011 11th IEEE International Conference on Nanotechnology10.1109/NANO.2011.6144434(500-503)Online publication date: Aug-2011
  • Show More Cited By

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    cover image ACM Conferences
    GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI
    May 2009
    558 pages
    ISBN:9781605585222
    DOI:10.1145/1531542
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 10 May 2009

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    Author Tags

    1. d3l
    2. dynamic
    3. full-adder
    4. reliability
    5. sub-threshold

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    Cited By

    View all
    • (2013)Designing Dynamic Carry Skip Adders: Analysis and ComparisonCircuits, Systems, and Signal Processing10.1007/s00034-013-9688-y33:4(1019-1034)Online publication date: 31-Oct-2013
    • (2012)Undergraduate Curriculum Development for Digital Integrated Circuit DesignCreative Education10.4236/ce.2012.32612803:06(856-858)Online publication date: 2012
    • (2011)Highly reliable and low-power full adder cell2011 11th IEEE International Conference on Nanotechnology10.1109/NANO.2011.6144434(500-503)Online publication date: Aug-2011
    • (2010)Threshold Voltage Variations Make Full Adders Reliabilities SimilarIEEE Transactions on Nanotechnology10.1109/TNANO.2010.20665739:6(664-667)Online publication date: 1-Nov-2010
    • (2010)Device-level reliability of several full adder cells10th IEEE International Conference on Nanotechnology10.1109/NANO.2010.5697865(1082-1087)Online publication date: Aug-2010
    • (2010)Data driven DCVSL: A clockless approach to dynamic differential circuit design2010 53rd IEEE International Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2010.5548907(640-643)Online publication date: Aug-2010
    • (2010)8-Bit sub threshold adders in 32nm CMOS technology for2010 Second International conference on Computing, Communication and Networking Technologies10.1109/ICCCNT.2010.5591637(1-6)Online publication date: Jul-2010

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