Dirk Koch
Abstract
In this work, we present hardware decompression accelerators for widening the bottleneck between slow nonvolatile memories on the one side and high-speed FPGA configuration interfaces and fast softcore CPUs on the other side. We discuss different compression algorithms suitable for a hardware accelerated decompression on FPGAs as well as on CPLDs. The algorithms will be investigated with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second under optimal conditions while only requiring slightly more than a hundred lookup tables. We will evaluate how these decompressors perform on configuration bitstreams for different FPGAs as well as for softcore CPU binaries.
- Altera Inc. 2007a. Enhanced configuration devices (EPC4, EPC8 & EPC16) data sheet.Google Scholar
- Altera Inc. 2007b. Alera devices. www.altera.com/products/devices/dev-index.jsp.Google Scholar
- Bobda, C., Majer, M., Ahmadinia, A., Haller, T., Linarth, A., and Teich, J. 2005. Increasing the flexibility in FPGA-Based reconfigurable platforms: The Erlangen slot machine. In Proceedings of the Conference on Field-Programmable Technology (FPT). 37--42.Google Scholar
- Dandalis, A. and Prasanna, V. K. 2001. Configuration compression for FPGA-based embedded systems. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA’01). 173--182. Google ScholarDigital Library
- Department of Computer Science 12. Bitstream Compression Benchmark http://www.reconets.de/bitstreamcompression/.Google Scholar
- Hauck, S. and Wilson, W. D. 1999. Runlength compression techniques for FPGA configurations. In Proceedings of the Conference Field-Programmable Custom Computing Machines. 286--287. Google ScholarDigital Library
- Heun, V. 2003. Grund legende Algorithmen. Vieweg.Google Scholar
- Hübner, M., Ullman, M., Weissel, F., and Becker, J. 2004. Real-time configuration code decompression for dynamic FPGA self-reconfigurations. In Proceedings of the 11th Reconfigurable Architectures Workshop (RAW’04).Google Scholar
- Hübner, M., Ullman, M., Weissel, F., and Becker, J. 2005. Real-time configuration code decompression for dynamic FPGA self-reconfiguration: Evaluation and implementation. EURASIP J. Embed. Syst. 1, 11.Google Scholar
- Huffman, D. A. 1952. A method for the construction of minimum-redundancy codes. Proc. IRE 40, 9, 1098--1101.Google ScholarCross Ref
- Koch, D. and Teich, J. 2004. Platform-independent methodology for partial reconfiguration. In Proceedings of the 1st Conference on Computing Frontiers. ACM Press, 398--403. Google ScholarDigital Library
- Koch, D., Beckhoff, C., and Teich, J. 2007. Bitstream decompression for high speed FPGA configuration from slow memories. In Proceedings of International Conference on Field-Programmable Technology (ICFPT’07). IEEE, 161--168.Google Scholar
- Koch, D., Körber, M., and Teich, J. 2006. Searching RC5-Keys with distributed reconfigurable computing. In Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’06). CSREA Press, 42--48.Google Scholar
- Li, Z. and Hauck, S. 1999. Don’t care discovery for FPGA configuration compression. In Proceedings of the ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays (FPGA’99). ACM Press. Google ScholarDigital Library
- Li, Z. and Hauck, S. 2001. Configuration compression for Virtex FPGAs. In Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE Computer Society, 147--159. Google ScholarDigital Library
- OpenCores. Opencores homepage. http://www.opencores.org.Google Scholar
- Pan, H, Mitra, T., and Wong, W.-F. 2004. Configuration bitstream compression for dynamically reconfigurable FPGAs. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’04). 766--773. Google ScholarDigital Library
- Salomon, D. 2004. Data Compression - The Complete Reference. Springer. Google ScholarDigital Library
- Storer, J. A. and Szymanski, T. G. 1982. Data compression via textual substitution. J. ACM 29, 4, 928--951. Google ScholarDigital Library
- Wetekam, G. and Lutz, B. 2005. Hardware-Implementierung einer 3D-Huffman-Decodierung für dynamische Volumendaten. In Proceedings of the Hardware for Visual Computing Workshop.Google Scholar
- Xilinx Inc. 2005. Virtex-II Platform FPGA User Guide. Xilinx.Google Scholar
- Xilinx Inc. 2007a. Xilinx: Silicon devices. www.xilinx.com/products/silicon_solutions/.Google Scholar
- Xilinx Inc. 2007b. Platform flash in-system programmable configuration PROMs.Google Scholar
- Ziv, J. and Lempel, A. 1977. A universal algorithm for sequential data compression. IEEE Trans. Inform. Theory 23, 3, 337--343.Google ScholarDigital Library
Index Terms
- Hardware Decompression Techniques for FPGA-Based Embedded Systems
Recommendations
Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation
Just-In-Time (JIT) compilation is frequently used in software engineering to accelerate program execution. Parts of the code are translated to machine code at runtime to speedup their execution by exploiting local and dynamic information of the ...
Hardware accelerated FPGA placement
A key advantage of field-programmable gate arrays (FPGAs) over full-custom and semi-custom devices is that they provide relatively quick implementation from concept to physical realization. However, as modern FPGAs reach close to one million logic ...
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP ...
Comments