research-article

Free access

Statistical analysis of circuit timing using majorization

Authors:

Michael Orshansky,

Wei-Shen WangAuthors Info & Claims

Communications of the ACM, Volume 52, Issue 8

Pages 95 - 100

https://doi.org/10.1145/1536616.1536641

Published: 01 August 2009 Publication History

All formats PDF

References

[1]

Agarwal, A., Zolotov, V., Blaauw, D.T. Statistical timing analysis using bounds and selective enumeration. IEEE Trans. Comp. Aided Des. Integr. Circuits Syst. 22, 9 (2003), 1243--1260.

Digital Library

Google Scholar

[2]

Bernstein, K., Frank, D.J., Gattiker, A.E., Haensch, W., Ji, B.L., Nassif, S.R., Nowak, E.J., Pearson, D.J., Rohrer, N.J. High-performance CMOS variability in the 65-nm regime and beyond. IBM J. Res. Dev. 50, 4 (2006), 433--449.

Digital Library

Google Scholar

[3]

Chang, H., Sapatnekar, S.S. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In Proceedings of the International Conference on Computer-Aided Design (San Jose, CA, 2003).

Digital Library

Google Scholar

[4]

Clark, C.E. The greatest of a finite set of random variables. Oper. Res. 9, 2 (1961), 85--91.

Digital Library

Google Scholar

[5]

Hassoun, S., Sasao, T. Logic Synthesis and Verification. Kluwer Academic Publishers, New York, 2002.

Digital Library

Google Scholar

[6]

Hitchcock, R.B. Timing verification and the timing analysis program. In Proceedings of the 19th Conference on Design Automation (Piscataway, NJ, 1982).

Digital Library

Google Scholar

[7]

Jacobs, E.T.A.F., Berkelaar, M.R.C.M. Gate sizing using a statistical delay model. In Proceedings of the Conference on Design, Automation and Test in Europe (Paris, France, 2000).

Digital Library

Google Scholar

[8]

Jess, J.A.G., Kalafala, K., Naidu, S.R., Otten, R.H.J.M., Visweswariah, C. Statistical timing for parametric yield prediction of digital integrated circuits. In Proceedings of the 40th Conference on Design Automation (Anaheim, CA, 2003).

Digital Library

Google Scholar

[9]

Jyu, H.F., Malik, S., Devadas, S., Keutzer, K.W. Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI Syst. 1, 2 (1993), 126--137.

Digital Library

Google Scholar

[10]

Marshall, A.W., Olkin, I. Inequalities: Theory of Majorization and Its Applications. Academic Press, New York, 1979.

Google Scholar

[11]

Moretti G. CLK Design Automation introduces Amber FX Analyzer, EDA Design Line. Retrieved on May 22, 2009, http://www.edadesignline.com/.

Google Scholar

[12]

Nadas, A. Probabilistic PERT. IBM J. Res. Dev. 23, 3 (1979), 339--347.

Digital Library

Google Scholar

[13]

Orshansky, M., Nassif, S., Boning, D. Design for Manufacturability and Statistical Design: A Constructive Approach. Springer, New York, 2008.

Digital Library

Google Scholar

[14]

Ramalingam, A., Nam, G., Singh, A.K., Orshansky, M., Nassif, S.R., Pan, D.Z. An accurate sparse matrix based framework for statistical static timing analysis. In Proceedings of the International Conference on Computer-Aided Design (San Jose, California, 2006).

Digital Library

Google Scholar

[15]

Robillard, P., Trahan M. The completion time of PERT networks. Oper. Res. 25, 1 (1977), 15--29.

Digital Library

Google Scholar

[16]

Tong, Y.L. Probability Inequalities in Multivariate Distributions. Academic Press, New York, 1980.

Google Scholar

[17]

Visweswariah, C., Ravindran, K., Kalafala, K., Walker, S.G., Narayan, S. First-order incremental block-based statistical timing analysis. In Proceedings of the 41st Conference on Design Automation (San Diego, CA, 2004).

Digital Library

Google Scholar

[18]

Wang, W.S., Orshansky, M. Path-based statistical timing analysis handling arbitrary delay correlations: theory and implementation. IEEE Trans. Comp. Aided Des. Integr. Circuits Syst. 25, 12 (2006), 2976--2988.

Digital Library

Google Scholar

[19]

Yen, S.H., Du, D.H., Ghanta, S. Efficient algorithms for extracting the K most critical paths in timing analysis. In Proceedings of the 26th Conference on Design Automation (Las Vegas, NV, 1989).

Digital Library

Google Scholar

Cited By

View all

Yang YJha N(2014)FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229388622:12(2462-2475)Online publication date: Dec-2014
https://doi.org/10.1109/TVLSI.2013.2293886
Yang YJha N(2013)Fin PrinProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.213(350-355)Online publication date: 5-Jan-2013
https://dl.acm.org/doi/10.1109/VLSID.2013.213

Index Terms

Statistical analysis of circuit timing using majorization
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Model verification and validation
2. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Logic circuits

Recommendations

Latch modeling for statistical timing analysis
DATE '08: Proceedings of the conference on Design, automation and test in Europe

Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new latch delay model in the context of SSTA based on a new perspective of latch ...
On Timing Model Extraction and Hierarchical Statistical Timing Analysis

In this paper, we investigate the challenges of applying statistical static timing analysis in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and ...
A statistical static timing analysis considering correlations between delays
ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

In this paper, we present a new algorithm for the statistical static timing analysis of a CMOS combinatorial circuit, which can treat correlations of arrival times of input signals to a logic gate and correlations of switching delays in a logic gate. We ...

Comments

Information & Contributors

Information

Published In

Communications of the ACM Volume 52, Issue 8

A Blind Person's Interaction with Technology

August 2009

132 pages

ISSN:0001-0782

EISSN:1557-7317

DOI:10.1145/1536616

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 2009

Published in CACM Volume 52, Issue 8

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article
Popular
Refereed

Funding Sources

Division of Computing and Communication Foundations

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
4,819
Total Downloads

Downloads (Last 12 months)213
Downloads (Last 6 weeks)55

Reflects downloads up to 01 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Yang YJha N(2014)FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229388622:12(2462-2475)Online publication date: Dec-2014
https://doi.org/10.1109/TVLSI.2013.2293886
Yang YJha N(2013)Fin PrinProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.213(350-355)Online publication date: 5-Jan-2013
https://dl.acm.org/doi/10.1109/VLSID.2013.213

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Digital Edition

View this article in digital edition.

Digital Edition

Magazine Site

View this article on the magazine site (external)

Magazine Site

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

References

Cited By

Index Terms

Recommendations

Latch modeling for statistical timing analysis

On Timing Model Extraction and Hierarchical Statistical Timing Analysis

A statistical static timing analysis considering correlations between delays

Comments

Information

Published In

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Funding Sources

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Digital Edition

Magazine Site

Login options

Full Access

Share

Share this Publication link

Share on social media

Affiliations