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Statistical analysis of circuit timing using majorization

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Michael Orshansky,

Wei-Shen WangAuthors Info & Claims

Communications of the ACM, Volume 52, Issue 8

Pages 95 - 100

https://doi.org/10.1145/1536616.1536641

Published: 01 August 2009 Publication History

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Cited By

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Yang YJha N(2014)FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229388622:12(2462-2475)Online publication date: Dec-2014
https://doi.org/10.1109/TVLSI.2013.2293886
Yang YJha N(2013)Fin PrinProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.213(350-355)Online publication date: 5-Jan-2013
https://dl.acm.org/doi/10.1109/VLSID.2013.213

Index Terms

Statistical analysis of circuit timing using majorization
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Model verification and validation
2. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Logic circuits

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Communications of the ACM Volume 52, Issue 8

A Blind Person's Interaction with Technology

August 2009

132 pages

ISSN:0001-0782

EISSN:1557-7317

DOI:10.1145/1536616

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 August 2009

Published in CACM Volume 52, Issue 8

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Yang YJha N(2014)FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229388622:12(2462-2475)Online publication date: Dec-2014
https://doi.org/10.1109/TVLSI.2013.2293886
Yang YJha N(2013)Fin PrinProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.213(350-355)Online publication date: 5-Jan-2013
https://dl.acm.org/doi/10.1109/VLSID.2013.213

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Latch modeling for statistical timing analysis

On Timing Model Extraction and Hierarchical Statistical Timing Analysis

A statistical static timing analysis considering correlations between delays

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