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Statistical analysis of circuit timing using majorization

Published: 01 August 2009 Publication History
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Cited By

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  • (2014)FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229388622:12(2462-2475)Online publication date: Dec-2014
  • (2013)Fin PrinProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.213(350-355)Online publication date: 5-Jan-2013

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cover image Communications of the ACM
Communications of the ACM  Volume 52, Issue 8
A Blind Person's Interaction with Technology
August 2009
132 pages
ISSN:0001-0782
EISSN:1557-7317
DOI:10.1145/1536616
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 August 2009
Published in CACM Volume 52, Issue 8

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View all
  • (2014)FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229388622:12(2462-2475)Online publication date: Dec-2014
  • (2013)Fin PrinProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.213(350-355)Online publication date: 5-Jan-2013

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