research-article

SlackSim: a platform for parallel simulations of CMPs on CMPs

Authors:

Murali Annavaram,

Michel DuboisAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 37, Issue 2

Pages 20 - 29

https://doi.org/10.1145/1577129.1577134

Published: 23 July 2009 Publication History

Abstract

The fast simulation of chip multiprocessors (CMPs) presents a critical challenge to the architecture research community as both industry and academia shift their research focus to multicore design. Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation paradigm of simulating each core of a target CMP in one thread and then spreading the threads across the hardware thread contexts of a host CMP. We implement several parallel simulation schemes using POSIX Threads (Pthreads). We start with cycle-by-cycle simulation and then relax the synchronization condition in various schemes, which we call slack simulations.

In slack simulations, the Pthreads simulating different simulated cores do not synchronize after each simulated cycle, but rather they are given some slack. The slack is the difference in cycle between the simulated times of any two target cores. Small slacks, such as a few cycles, greatly improve the efficiency of parallel CMP simulations, with no or negligible simulation error. We have developed a simulation framework called SlackSim to experiment with various slack simulation schemes. Unlike previous attempts to parallelize multiprocessor simulations on distributed memory machines, SlackSim takes advantage of the efficient sharing of data in the host CMP architecture.

We demonstrate the efficiency and accuracy of some well known slack simulation schemes and of some new ones on SlackSim running on a state-of-the-art CMP platform.

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 37, Issue 2

May 2009

69 pages

ISSN:0163-5964

DOI:10.1145/1577129

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Copyright © 2009 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 July 2009

Published in SIGARCH Volume 37, Issue 2

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https://doi.org/10.1109/ISCA59077.2024.00046
Bremer MPatra NNguyen TVasudevan DChan C(2023)Benefits of Optimistic Parallel Discrete Event Simulation for Network-on-Chip Simulation2023 IEEE/ACM 27th International Symposium on Distributed Simulation and Real Time Applications (DS-RT)10.1109/DS-RT58998.2023.00013(30-39)Online publication date: 4-Oct-2023
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