abstract

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM

Authors:

Ki Chul Chun,

Pulkit Jain,

Chris H. KimAuthors Info & Claims

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

Pages 119 - 120

https://doi.org/10.1145/1594233.1594261

Published: 19 August 2009 Publication History

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Abstract

A logic-compatible low power eDRAM is demonstrated in 65nm CMOS achieving a retention time of 1.25msec and a static power dissipation of 91.3µW/Mb at 0.9V, 85ºC. A boosted 3T gain cell enhances data retention time and read speed. A regulated bit-line write scheme and a read reference bias generator mitigate write disturbance issues and improve tolerance to PVT variations.

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Cited By

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Hu JZhuge QXue CTseng WSha E(2014)Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processorsACM Transactions on Embedded Computing Systems10.1145/256001913:4(1-25)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2560019
Jingtong Hu Xue CQingfeng Zhuge Wei-Che Tseng Sha E(2011)Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763127(1-6)Online publication date: Mar-2011
https://doi.org/10.1109/DATE.2011.5763127

Index Terms

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

August 2009

452 pages

ISBN:9781605586847

DOI:10.1145/1594233

General Chairs:
Jörg Henkel
University of Karlsruhe
,
Ali Keshavarzi
Taiwan Semiconductor Manufacturing Company
,
Program Chairs:
Naehyuck Chang
Seoul National University
,
Tahir Ghani
Intel Corporation

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Association for Computing Machinery

New York, NY, United States

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Published: 19 August 2009

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ISLPED'09

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ISLPED'09: International Symposium on Low Power Electronics and Design

August 19 - 21, 2009

CA, San Fancisco, USA

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ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Hu JZhuge QXue CTseng WSha E(2014)Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processorsACM Transactions on Embedded Computing Systems10.1145/256001913:4(1-25)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2560019
Jingtong Hu Xue CQingfeng Zhuge Wei-Che Tseng Sha E(2011)Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763127(1-6)Online publication date: Mar-2011
https://doi.org/10.1109/DATE.2011.5763127

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Recommendations

Energy efficient Phase Change Memory based main memory for future high performance systems

Adaptive refresh structure for gain cell embedded DRAM

FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nm

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