ABSTRACT
A logic-compatible low power eDRAM is demonstrated in 65nm CMOS achieving a retention time of 1.25msec and a static power dissipation of 91.3µW/Mb at 0.9V, 85ºC. A boosted 3T gain cell enhances data retention time and read speed. A regulated bit-line write scheme and a read reference bias generator mitigate write disturbance issues and improve tolerance to PVT variations.
- N. Kim, et al., "Leakage Current: Moore's Law Meets Static Power", IEEE Computer, Vol. 36, Issue 12, pp. 68--75, Dec. 2003. Google ScholarDigital Library
- S. Rusu, et al., "A 65-nm Dual-Core Multithreaded Xeon Processor With 16-MB L3 Cahce", IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 17--25, Jan. 2007.Google ScholarCross Ref
- R. E. Matick, S. E Schuster, "Logic-based eDRAM: Origins and rationale for use", IBM Journal of Research and Development, vol. 49, no. 1, pp. 145--165, Jan. 2005. Google ScholarDigital Library
- J. Barth, et al., "A 500MHz Random Cycle, 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier", International Solid-State Circuits Conference, pp. 486--487, Feb 2007.Google Scholar
- S. Romanovsky, et al., "A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS", International Solid-State Circuits Conference, pp. 270--271, Feb 2008.Google Scholar
- W. Luk, et al., "A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time", VLSI Circuits Symposium, pp. 184--185, Jun 2006.Google Scholar
- D. Somasekhar, et al., "2GHz 2Mbit 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process", International Solid-State Circuits Conference, pp. 274--275, Feb 2008.Google Scholar
- A. Agarwal, et al., "A single Vt low-leakage gated-ground cache for deep submicron", IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 319--328, Feb 2003.Google ScholarCross Ref
- C. Kim, et al., "PVT-Aware Leakage Reduction for On-Die Caches With Improved Read Stability", IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 170-178, Jan 2006.Google ScholarCross Ref
- E. Seevinck, et al., "Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's", IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 525--536, Apr 1991.Google ScholarCross Ref
- J. Sim, et al., "A 1.8-V 128-Mb Mobile DRAM With Double Boosting Pump, Hybrid Current Sense Amplifier, and Dual-Referenced Adjustment Scheme for Temperature Sensor", IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 631--639, Apr 2003.Google ScholarCross Ref
Index Terms
- A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM
Recommendations
Energy efficient Phase Change Memory based main memory for future high performance systems
IGCC '11: Proceedings of the 2011 International Green Computing Conference and WorkshopsPhase Change Memory (PCM) has recently attracted a lot of attention as a scalable alternative to DRAM for main memory systems. As the need for high-density memory increases, DRAM has proven to be less attractive from the point of view of scaling and ...
Adaptive refresh structure for gain cell embedded DRAM
Recently, gain cell eDRAMs have been attractive alternatives to SRAM and 1T1C DRAM for high density and logic-compatible embedded memories. The refresh period is traditionally determined according to the highest working temperature and worst-case access ...
FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nm
AbstractThis paper presents an ultra-low power 3T gain-cell embedded DRAM (GC-eDRAM) cell in fin field-effect transistor (FinFET). This memory structure uses fast and low leakage FinFET transistors to improve frequent refresh issue and reduce retention ...
Comments