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The opportunity cost of low power design: a case study in circuit tuning

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Joshua FriedrichAuthors Info & Claims

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

Pages 133 - 138

https://doi.org/10.1145/1594233.1594265

Published: 19 August 2009 Publication History

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Abstract

The time-to-market pressures combined with the immense power reduction design space of VLSI design call for an evaluation of power savings opportunities prior to the investment in design effort. This paper presents an estimation methodology for predicting the power savings of circuit tuning for an industrial chip design project. A comparison between the estimated and actual power savings realized through tuning over 100 macros on the chip validates the accuracy of this estimation methodology.

References

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Ziegler MPuri RPhilhower BFranch RLuk WLeenstra JVerwegen PFricke NGristede GFluhr EZyuban V(2014)POWER8 design methodology innovations for improving productivity and reducing powerProceedings of the IEEE 2014 Custom Integrated Circuits Conference10.1109/CICC.2014.6946042(1-9)Online publication date: Sep-2014
https://doi.org/10.1109/CICC.2014.6946042
Ziegler MGristede GZyuban VChou PHuang RXie YKarnik T(2013)Power reduction by aggressive synthesis design space explorationProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648765(421-426)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.5555/2648668.2648765
Ziegler MGristede GZyuban V(2013)Power reduction by aggressive synthesis design space explorationInternational Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2013.6629335(421-426)Online publication date: Sep-2013
https://doi.org/10.1109/ISLPED.2013.6629335
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Index Terms

The opportunity cost of low power design: a case study in circuit tuning
1. Hardware
  1. Integrated circuits

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Published In

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

August 2009

452 pages

ISBN:9781605586847

DOI:10.1145/1594233

General Chairs:
Jörg Henkel
University of Karlsruhe
,
Ali Keshavarzi
Taiwan Semiconductor Manufacturing Company
,
Program Chairs:
Naehyuck Chang
Seoul National University
,
Tahir Ghani
Intel Corporation

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 19 August 2009

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ISLPED'09: International Symposium on Low Power Electronics and Design

August 19 - 21, 2009

CA, San Fancisco, USA

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ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Ziegler MPuri RPhilhower BFranch RLuk WLeenstra JVerwegen PFricke NGristede GFluhr EZyuban V(2014)POWER8 design methodology innovations for improving productivity and reducing powerProceedings of the IEEE 2014 Custom Integrated Circuits Conference10.1109/CICC.2014.6946042(1-9)Online publication date: Sep-2014
https://doi.org/10.1109/CICC.2014.6946042
Ziegler MGristede GZyuban VChou PHuang RXie YKarnik T(2013)Power reduction by aggressive synthesis design space explorationProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648765(421-426)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.5555/2648668.2648765
Ziegler MGristede GZyuban V(2013)Power reduction by aggressive synthesis design space explorationInternational Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2013.6629335(421-426)Online publication date: Sep-2013
https://doi.org/10.1109/ISLPED.2013.6629335
Zyuban VFriedrich JGonzalez CRao RBrown MZiegler MJacobson HIslam SChu SKartschoke PFiorenza GBoersma MCulp J(2011)Power optimization methodology for the IBM POWER7 microprocessorIBM Journal of Research and Development10.1147/JRD.2011.211041055:3(267-275)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1147/JRD.2011.2110410

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Recommendations

Variable input delay CMOS logic for low power design

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements

Two-level logic minimization for low power

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