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An optimization strategy for low energy and high performance for the on-chip interconnect signalling

Published: 19 August 2009 Publication History

Abstract

Coupling capacitance between adjacent wires in on-chip interconnect significantly increases the average transition energy dissipation, and the maximum delay. This paper proposed a novel encoding scheme to, further, reduce the coupling energy dissipation, and delay. Specifically for 65nm CMOS technology, we present an 8-bit to 10-bit equivalent solution that reduces the energy dissipation by 55%, and delay by 24%, without any additional area penalty, while requiring a less complex circuit overhead when compared with transition pattern coding (TPC) scheme.

References

[1]
N. S. A. Elkammar and S. Vemuru. Bus encoding scheme to eliminate unwanted signal transitions. In Proceedings of Int. Workshop on Electronic Design, Test and Applications (DELTA), Kuala Lumpur, Malaysia, pages 472--480, Washington, DC, USA, Jan. 2006. IEEE Computer Society.
[2]
V. G. H. Zhang and J. M. Rabaey. Low-swing on-chip signaling techniques: effectiveness androbustness. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 8(3):264--272, 2000.
[3]
N. Menezes and L. Pillegi. Analyzing on-chip interconnect effects. In Design of High Performance Microprocessors Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox Eds.(Piscataway, NJ: IEEE Press):ch. 16, 2001 ed.
[4]
Nanoscale Integration and Modeling (NIMO) Group, Arizona State University. Predictive technology model (ptm), 2007. http://www.eas.asu.edu/ ptm/.
[5]
J. Natesan and D. Radhakrishnan. Shift invert coding (sinv) for low power vlsi. In Euromicro Sym. on Digital System Design, (DSD), pages 190--194, Aug. 2004.
[6]
K. Sainarayanan, J. Ravindra, and M. Srinivas. A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in vlsi interconnects. In IEEE Int. Symp. on Cir. and Sys., (ISCAS), May 2006.
[7]
P. Sotiriadis and A. Chandrakasan. Reducing bus delay in submicron technology using coding. In IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pages 109--114, Jan. 2001.
[8]
P. Sotiriadis and A. Chandrakasan. A bus energy model for deep submicron technology. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 10(3):341--350, Jun 2002.
[9]
P. Sotiriadis and A. Chandrakasan. Bus energy reduction by transition pattern coding using a detailed deep submicrometer bus model. IEEE Trans. on Circuits and Systems I, 50(10):1280--1295, Oct. 2003.
[10]
M. Stan and W. Burleson. Bus-invert coding for low-power i/o. IEEE Trans. on, Very Large Scale Integration (VLSI) Systems, 3(1):49--58, Mar 1995.
[11]
S.-C. Wong, G.-Y. Lee, and D.-J. Ma. Modeling of interconnect capacitance, delay, and crosstalk in vlsi. Semiconductor Manufacturing, IEEE Transactions on, 13(1):108--111, Feb 2000

Cited By

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  • (2017)Analysis and design of serial error correction code with crosstalk avoidance technique2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE.2017.7946606(1-4)Online publication date: Apr-2017
  • (2016)A Quadro Coding Technique to Reduce Self Transitions in VLSI Interconnects2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)10.1109/iNIS.2016.033(98-101)Online publication date: Dec-2016
  • (2010)A hybrid equivalent-bit spacing scheme for low energy and high performance for bus signalling2010 53rd IEEE International Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2010.5548686(209-212)Online publication date: Aug-2010

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  1. An optimization strategy for low energy and high performance for the on-chip interconnect signalling

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    cover image ACM Conferences
    ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design
    August 2009
    452 pages
    ISBN:9781605586847
    DOI:10.1145/1594233
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 19 August 2009

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    Author Tags

    1. interconnect signaling
    2. low energy

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    ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;
    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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    • (2017)Analysis and design of serial error correction code with crosstalk avoidance technique2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE.2017.7946606(1-4)Online publication date: Apr-2017
    • (2016)A Quadro Coding Technique to Reduce Self Transitions in VLSI Interconnects2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)10.1109/iNIS.2016.033(98-101)Online publication date: Dec-2016
    • (2010)A hybrid equivalent-bit spacing scheme for low energy and high performance for bus signalling2010 53rd IEEE International Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2010.5548686(209-212)Online publication date: Aug-2010

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