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Challenges and opportunities in low-power design enablement

Published: 19 August 2009 Publication History

Abstract

At 32nm and beyond, SoC designs will become more challenging and achieving low-power targets requires a new working model between Design and Process teams. There are significant opportunities for lowering power at the interface of design and process technologies. This talk addresses these opportunities and discusses the critical role of Design Enablement function.

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  1. Challenges and opportunities in low-power design enablement

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    cover image ACM Conferences
    ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design
    August 2009
    452 pages
    ISBN:9781605586847
    DOI:10.1145/1594233

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    Association for Computing Machinery

    New York, NY, United States

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    Published: 19 August 2009

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    ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;
    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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