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Ultra low voltage CMOS

Published: 19 August 2009 Publication History

Abstract

Power dissipation is one of the major design concerns for nano-scale CMOS systems. In this talk I will first present ultra low voltage design challenges for both logic and memory considering different levels of design abstraction — device, circuit, and architecture. In the second part of the talk, I will present ultra-dynamic voltage scaling to have the maximum dynamic range of Vdd. Such adaptive supply scaling can provide the required performance at minimum power dissipation under varied load condition.

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  1. Ultra low voltage CMOS

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    cover image ACM Conferences
    ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design
    August 2009
    452 pages
    ISBN:9781605586847
    DOI:10.1145/1594233

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 19 August 2009

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    Author Tags

    1. adaptive supply scaling
    2. nano-scale cmos system
    3. ultra low voltage design
    4. ultra-dynamic voltage scaling

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    ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;
    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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